Commit ac9c5e92 authored by Robin Murphy's avatar Robin Murphy Committed by Joerg Roedel
Browse files

iommu/arm-smmu: Report IOMMU_CAP_CACHE_COHERENCY even betterer 



Although it's vanishingly unlikely that anyone would integrate an SMMU
within a coherent interconnect without also making the pagetable walk
interface coherent, the same effect happens if a coherent SMMU fails to
advertise CTTW correctly. This turns out to be the case on some popular
NXP SoCs, where VFIO started failing the IOMMU_CAP_CACHE_COHERENCY test,
even though IOMMU_CACHE *was* previously achieving the desired effect
anyway thanks to the underlying integration.

While those SoCs stand to gain some more general benefits from a
firmware update to override CTTW correctly in DT/ACPI, it's also easy
to work around this in Linux as well, to avoid imposing too much on
affected users - since the upstream client devices *are* correctly
marked as coherent, we can trivially infer their coherent paths through
the SMMU as well.

Reported-by: default avatarVladimir Oltean <vladimir.oltean@nxp.com>
Fixes: df198b37 ("iommu/arm-smmu: Report IOMMU_CAP_CACHE_COHERENCY better")
Signed-off-by: default avatarRobin Murphy <robin.murphy@arm.com>
Tested-by: default avatarVladimir Oltean <vladimir.oltean@nxp.com>
Link: https://lore.kernel.org/r/d6dc41952961e5c7b21acac08a8bf1eb0f69e124.1671123115.git.robin.murphy@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent b7bfaa76

drivers/iommu/arm/arm-smmu/arm-smmu.c

+8 −2
Original line number Original line Diff line number Diff line
@@ -1316,8 +1316,14 @@ static bool arm_smmu_capable(struct device *dev, enum iommu_cap cap) 




	switch (cap) {

	switch (cap) {

	case IOMMU_CAP_CACHE_COHERENCY:

	case IOMMU_CAP_CACHE_COHERENCY:

		/* Assume that a coherent TCU implies coherent TBUs */

		/*

		return cfg->smmu->features & ARM_SMMU_FEAT_COHERENT_WALK;

		 * It's overwhelmingly the case in practice that when the pagetable

		 * walk interface is connected to a coherent interconnect, all the

		 * translation interfaces are too. Furthermore if the device is

		 * natively coherent, then its translation interface must also be.

		 */

		return cfg->smmu->features & ARM_SMMU_FEAT_COHERENT_WALK ||

			device_get_dma_attr(dev) == DEV_DMA_COHERENT;

	case IOMMU_CAP_NOEXEC:

	case IOMMU_CAP_NOEXEC:

		return true;

		return true;

	default:

	default: