Commit ac91be97 authored by Ping-Ke Shih's avatar Ping-Ke Shih Committed by Kalle Valo
Browse files

rtw89: 8852c: rfk: add RX DCK 



RX DCK is receiver DC calibration. Do this calibration when bringing up
interface and going to run on AP channel.

Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220502235408.15052-7-pkshih@realtek.com
parent 30052c5a

drivers/net/wireless/realtek/rtw89/reg.h

+8 −1
Original line number Diff line number Diff line
@@ -3312,17 +3312,24 @@ 
#define RR_RXIQGEN_ATTL GENMASK(12, 8)

#define RR_RXIQGEN_ATTH GENMASK(14, 13)

#define RR_RXBB2 0x8f

#define RR_EN_TIA_IDA GENMASK(11, 10)

#define RR_RXBB2_DAC_EN BIT(13)

#define RR_RXBB2_CKT BIT(12)

#define RR_EN_TIA_IDA GENMASK(11, 10)

#define RR_RXBB2_IDAC GENMASK(11, 9)

#define RR_RXBB2_EBW GENMASK(6, 5)

#define RR_XALNA2 0x90

#define RR_XALNA2_SW GENMASK(1, 0)

#define RR_DCK 0x92

#define RR_DCK_DONE GENMASK(7, 5)

#define RR_DCK_FINE BIT(1)

#define RR_DCK_LV BIT(0)

#define RR_DCK1 0x93

#define RR_DCK1_CLR GENMASK(3, 0)

#define RR_DCK1_SEL BIT(3)

#define RR_DCK2 0x94

#define RR_DCK2_CYCLE GENMASK(7, 2)

#define RR_DCKC 0x95

#define RR_DCKC_CHK BIT(3)

#define RR_MIXER 0x9f

#define RR_MIXER_GN GENMASK(4, 3)

#define RR_XTALX2 0xb8

drivers/net/wireless/realtek/rtw89/rtw8852c.c

+2 −0
Original line number Diff line number Diff line
@@ -1779,12 +1779,14 @@ static void rtw8852c_rfk_init(struct rtw89_dev *rtwdev) 


	rtw8852c_rck(rtwdev);

	rtw8852c_dack(rtwdev);

	rtw8852c_rx_dck(rtwdev, RTW89_PHY_0, false);

}



static void rtw8852c_rfk_channel(struct rtw89_dev *rtwdev)

{

	enum rtw89_phy_idx phy_idx = RTW89_PHY_0;



	rtw8852c_rx_dck(rtwdev, phy_idx, false);

	rtw8852c_tssi(rtwdev, phy_idx);

	rtw89_fw_h2c_rf_ntfy_mcc(rtwdev);

}

drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.c

+67 −0
Original line number Diff line number Diff line
@@ -505,6 +505,42 @@ static void _rck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) 
		    rtw89_read_rf(rtwdev, path, RR_RCKS, RFREG_MASK));

}



static void _rx_dck_toggle(struct rtw89_dev *rtwdev, u8 path)

{

	int ret;

	u32 val;



	rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0);

	rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1);



	ret = read_poll_timeout_atomic(rtw89_read_rf, val, val,

				       2, 1000, false, rtwdev, path, 0x93, BIT(5));

	if (ret)

		rtw89_warn(rtwdev, "[RX_DCK] S%d RXDCK timeout\n", path);

	else

		rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RX_DCK] S%d RXDCK finish\n", path);



	rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0);

}



static void _set_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, u8 path,

			bool is_afe)

{

	u8 res;



	rtw89_write_rf(rtwdev, path, RR_DCK1, RR_DCK1_CLR, 0x0);



	_rx_dck_toggle(rtwdev, path);

	if (rtw89_read_rf(rtwdev, path, RR_DCKC, RR_DCKC_CHK) == 0)

		return;

	res = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_DONE);

	if (res > 1) {

		rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_IDAC, res);

		_rx_dck_toggle(rtwdev, path);

		rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_IDAC, 0x1);

	}

}



static void _tssi_set_sys(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,

			  enum rtw89_rf_path path)

{
@@ -1671,6 +1707,37 @@ void rtw8852c_dack(struct rtw89_dev *rtwdev) 
	rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_STOP);

}



#define RXDCK_VER_8852C 0xe



void rtw8852c_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, bool is_afe)

{

	u8 path, kpath;

	u32 rf_reg5;



	kpath = _kpath(rtwdev, phy);

	rtw89_debug(rtwdev, RTW89_DBG_RFK,

		    "[RX_DCK] ****** RXDCK Start (Ver: 0x%x, Cv: %d) ******\n",

		    RXDCK_VER_8852C, rtwdev->hal.cv);



	for (path = 0; path < 2; path++) {

		rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);

		if (!(kpath & BIT(path)))

			continue;



		if (rtwdev->is_tssi_mode[path])

			rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13),

					       B_P0_TSSI_TRK_EN, 0x1);

		rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);

		rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);

		_set_rx_dck(rtwdev, phy, path, is_afe);

		rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);



		if (rtwdev->is_tssi_mode[path])

			rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13),

					       B_P0_TSSI_TRK_EN, 0x0);

	}

}



void rtw8852c_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)

{

	u32 i, path = RF_PATH_A, path_max = RF_PATH_NUM_8852C;

drivers/net/wireless/realtek/rtw89/rtw8852c_rfk.h

+1 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 


void rtw8852c_rck(struct rtw89_dev *rtwdev);

void rtw8852c_dack(struct rtw89_dev *rtwdev);

void rtw8852c_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, bool is_afe);

void rtw8852c_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy);

void rtw8852c_tssi_scan(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy);

void rtw8852c_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, u8 phy_idx);