Unverified Commit ac8d0b90 authored by Zihao Yu's avatar Zihao Yu Committed by Palmer Dabbelt
Browse files

riscv,entry: fix misaligned base for excp_vect_table 



In RV64, the size of each entry in excp_vect_table is 8 bytes. If the
base of the table is not 8-byte aligned, loading an entry in the table
will raise a misaligned exception. Although such exception will be
handled by opensbi/bbl, this still causes performance degradation.

Signed-off-by: default avatarZihao Yu <yuzihao@ict.ac.cn>
Reviewed-by: default avatarAnup Patel <anup@brainfault.org>
Signed-off-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
parent 285a76bb

arch/riscv/kernel/entry.S

+1 −0
Original line number Diff line number Diff line
@@ -447,6 +447,7 @@ ENDPROC(__switch_to) 
#endif



	.section ".rodata"

	.align LGREG

	/* Exception vector table */

ENTRY(excp_vect_table)

	RISCV_PTR do_trap_insn_misaligned