Commit ac6e9e3d authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-5.13-2021-05-26' of... 

Merge tag 'amd-drm-fixes-5.13-2021-05-26' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-5.13-2021-05-26:

amdgpu:
- MultiGPU fan fix
- VCN powergating fixes

amdkfd:
- Fix SDMA register offset error

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210527031831.4057-1-alexander.deucher@amd.com
parents c4681547 20ebbfd2

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

+6 −6
Original line number Diff line number Diff line
@@ -156,16 +156,16 @@ static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev, 
				mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;

		break;

	case 1:

		sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,

		sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,

				mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;

		break;

	case 2:

		sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA2, 0,

				mmSDMA2_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL;

		sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,

				mmSDMA2_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;

		break;

	case 3:

		sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA3, 0,

				mmSDMA3_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL;

		sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,

				mmSDMA3_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;

		break;

	}
@@ -450,7 +450,7 @@ static int hqd_sdma_dump_v10_3(struct kgd_dev *kgd, 
			engine_id, queue_id);

	uint32_t i = 0, reg;

#undef HQD_N_REGS

#define HQD_N_REGS (19+6+7+10)

#define HQD_N_REGS (19+6+7+12)



	*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);

	if (*dump == NULL)

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

+2 −0
Original line number Diff line number Diff line
@@ -172,6 +172,8 @@ static int jpeg_v2_0_hw_fini(void *handle) 
{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	cancel_delayed_work_sync(&adev->vcn.idle_work);



	if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&

	      RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))

		jpeg_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

+2 −2
Original line number Diff line number Diff line
@@ -187,14 +187,14 @@ static int jpeg_v2_5_hw_init(void *handle) 
static int jpeg_v2_5_hw_fini(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct amdgpu_ring *ring;

	int i;



	cancel_delayed_work_sync(&adev->vcn.idle_work);



	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {

		if (adev->jpeg.harvest_config & (1 << i))

			continue;



		ring = &adev->jpeg.inst[i].ring_dec;

		if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&

		      RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS))

			jpeg_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);

drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c

+2 −2
Original line number Diff line number Diff line
@@ -159,9 +159,9 @@ static int jpeg_v3_0_hw_init(void *handle) 
static int jpeg_v3_0_hw_fini(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct amdgpu_ring *ring;



	ring = &adev->jpeg.inst->ring_dec;

	cancel_delayed_work_sync(&adev->vcn.idle_work);



	if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&

	      RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))

		jpeg_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

+5 −1
Original line number Diff line number Diff line
@@ -231,9 +231,13 @@ static int vcn_v1_0_hw_fini(void *handle) 
{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	cancel_delayed_work_sync(&adev->vcn.idle_work);



	if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||

		RREG32_SOC15(VCN, 0, mmUVD_STATUS))

		(adev->vcn.cur_state != AMD_PG_STATE_GATE &&

		 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {

		vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE);

	}



	return 0;

}