Commit ac376dd8 authored by Xie Haocheng's avatar Xie Haocheng
Browse files

x86/cpufeatures: Fix abi breakage caused by NCAPINTS in cpufeature header file. 

amd inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I5S3WV


CVE: NA

-------------------------------------------------

The abi breakage is relate to commit: fb35d30f.

Signed-off-by: default avatarXie Haocheng <haocheng.xie@amd.com>
parent f459cf1e

arch/x86/include/asm/cpufeature.h

+2 −4
Original line number Diff line number Diff line
@@ -90,9 +90,8 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; 
	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 16, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 17, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 18, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 19, feature_bit) ||	\

	   REQUIRED_MASK_CHECK					  ||	\

	   BUILD_BUG_ON_ZERO(NCAPINTS != 20))

	   BUILD_BUG_ON_ZERO(NCAPINTS != 19))



#define DISABLED_MASK_BIT_SET(feature_bit)				\

	 ( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK,  0, feature_bit) ||	\
@@ -114,9 +113,8 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; 
	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 16, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 17, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 18, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 19, feature_bit) ||	\

	   DISABLED_MASK_CHECK					  ||	\

	   BUILD_BUG_ON_ZERO(NCAPINTS != 20))

	   BUILD_BUG_ON_ZERO(NCAPINTS != 19))



#define cpu_has(c, bit)							\

	(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 :	\

arch/x86/include/asm/cpufeatures.h

+8 −7
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ 
/*

 * Defines x86 CPU feature bits

 */

#define NCAPINTS			20	   /* N 32-bit words worth of info */

#define NCAPINTS			19     /* N 32-bit words worth of info */

#define NBUGINTS			1	   /* N 32-bit bug flags */



/*
@@ -399,6 +399,13 @@ 
#define X86_FEATURE_SUCCOR		(17*32+ 1) /* Uncorrectable error containment and recovery */

#define X86_FEATURE_SMCA		(17*32+ 3) /* Scalable MCA */



/* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19 */

#define X86_FEATURE_SME			(17*32+ 27) /* AMD Secure Memory Encryption */

#define X86_FEATURE_SEV			(17*32+ 28) /* AMD Secure Encrypted Virtualization */

#define X86_FEATURE_VM_PAGE_FLUSH	(17*32+ 29) /* "" VM Page Flush MSR is supported */

#define X86_FEATURE_SEV_ES		(17*32+ 30) /* AMD Secure Encrypted Virtualization - Encrypted State */

#define X86_FEATURE_SME_COHERENT	(17*32+31) /* "" AMD hardware-enforced cache coherency */



/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */

#define X86_FEATURE_AVX512_4VNNIW	(18*32+ 2) /* AVX-512 Neural Network Instructions */

#define X86_FEATURE_AVX512_4FMAPS	(18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
@@ -419,12 +426,6 @@ 
#define X86_FEATURE_CORE_CAPABILITIES	(18*32+30) /* "" IA32_CORE_CAPABILITIES MSR */

#define X86_FEATURE_SPEC_CTRL_SSBD	(18*32+31) /* "" Speculative Store Bypass Disable */



/* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19 */

#define X86_FEATURE_SME			(19*32+ 0) /* AMD Secure Memory Encryption */

#define X86_FEATURE_SEV			(19*32+ 1) /* AMD Secure Encrypted Virtualization */

#define X86_FEATURE_VM_PAGE_FLUSH	(19*32+ 2) /* "" VM Page Flush MSR is supported */

#define X86_FEATURE_SEV_ES		(19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */

#define X86_FEATURE_SME_COHERENT	(19*32+10) /* "" AMD hardware-enforced cache coherency */



/*

 * BUG word(s)

arch/x86/include/asm/disabled-features.h

+1 −2
Original line number Diff line number Diff line
@@ -107,7 +107,6 @@ 
			 DISABLE_ENQCMD)

#define DISABLED_MASK17	0

#define DISABLED_MASK18	0

#define DISABLED_MASK19	0

#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 20)

#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)



#endif /* _ASM_X86_DISABLED_FEATURES_H */

arch/x86/include/asm/required-features.h

+1 −2
Original line number Diff line number Diff line
@@ -101,7 +101,6 @@ 
#define REQUIRED_MASK16	0

#define REQUIRED_MASK17	0

#define REQUIRED_MASK18	0

#define REQUIRED_MASK19	0

#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 20)

#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)



#endif /* _ASM_X86_REQUIRED_FEATURES_H */

tools/arch/x86/include/asm/disabled-features.h

+1 −2
Original line number Diff line number Diff line
@@ -104,7 +104,6 @@ 
			 DISABLE_ENQCMD)

#define DISABLED_MASK17	0

#define DISABLED_MASK18	0

#define DISABLED_MASK19	0

#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 20)

#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)



#endif /* _ASM_X86_DISABLED_FEATURES_H */