Commit ac2743a7 authored by Iwona Winiarska's avatar Iwona Winiarska Committed by Greg Kroah-Hartman
Browse files

ARM: dts: aspeed: Add PECI controller nodes 



Add PECI controller nodes with all required information.

Co-developed-by: default avatarJae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Reviewed-by: default avatarJoel Stanley <joel@jms.id.au>
Acked-by: default avatarJoel Stanley <joel@jms.id.au>
Signed-off-by: default avatarJae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Signed-off-by: default avatarIwona Winiarska <iwona.winiarska@intel.com>
Link: https://lore.kernel.org/r/20220208153639.255278-4-iwona.winiarska@intel.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 0af618d6

arch/arm/boot/dts/aspeed-g4.dtsi

+11 −0
Original line number Diff line number Diff line
@@ -392,6 +392,17 @@ 
				};

			};



			peci0: peci-controller@1e78b000 {

				compatible = "aspeed,ast2400-peci";

				reg = <0x1e78b000 0x60>;

				interrupts = <15>;

				clocks = <&syscon ASPEED_CLK_GATE_REFCLK>;

				resets = <&syscon ASPEED_RESET_PECI>;

				cmd-timeout-ms = <1000>;

				clock-frequency = <1000000>;

				status = "disabled";

			};



			uart2: serial@1e78d000 {

				compatible = "ns16550a";

				reg = <0x1e78d000 0x20>;

arch/arm/boot/dts/aspeed-g5.dtsi

+11 −0
Original line number Diff line number Diff line
@@ -516,6 +516,17 @@ 
				};

			};



			peci0: peci-controller@1e78b000 {

				compatible = "aspeed,ast2500-peci";

				reg = <0x1e78b000 0x60>;

				interrupts = <15>;

				clocks = <&syscon ASPEED_CLK_GATE_REFCLK>;

				resets = <&syscon ASPEED_RESET_PECI>;

				cmd-timeout-ms = <1000>;

				clock-frequency = <1000000>;

				status = "disabled";

			};



			uart2: serial@1e78d000 {

				compatible = "ns16550a";

				reg = <0x1e78d000 0x20>;

arch/arm/boot/dts/aspeed-g6.dtsi

+11 −0
Original line number Diff line number Diff line
@@ -512,6 +512,17 @@ 
				status = "disabled";

			};



			peci0: peci-controller@1e78b000 {

				compatible = "aspeed,ast2600-peci";

				reg = <0x1e78b000 0x100>;

				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&syscon ASPEED_CLK_GATE_REF0CLK>;

				resets = <&syscon ASPEED_RESET_PECI>;

				cmd-timeout-ms = <1000>;

				clock-frequency = <1000000>;

				status = "disabled";

			};



			lpc: lpc@1e789000 {

				compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";

				reg = <0x1e789000 0x1000>;