Commit ac02dc34 authored by Eric Yang's avatar Eric Yang Committed by Alex Deucher
Browse files

drm/amd/display: Add periodic detection when zstate is enabled 



[Why]
When system is in Z10 HPD interrupts cannot fire, we may miss display
configuration changes.

[How]
When Zstate is enabled, if DMUB indicate DCN has lost power, do a
complete detection periodically.

Reviewed-by: default avatarNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: default avatarMikita Lipski <mikita.lipski@amd.com>
Signed-off-by: default avatarEric Yang <Eric.Yang2@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6513104b

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

+6 −0
Original line number Diff line number Diff line
@@ -793,4 +793,10 @@ void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz) 
       // FPGA programming for this clock in diags framework that

       // needs to go through dm layer, therefore leave dummy interace here

}





void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable)

{

	/* TODO: add peridic detection implementation */

}

#endif
 
 No newline at end of file

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

+2 −0
Original line number Diff line number Diff line
@@ -142,6 +142,7 @@ static void dcn31_update_clocks(struct clk_mgr *clk_mgr_base, 
		if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_ALLOW &&

				new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {

			dcn31_smu_set_Z9_support(clk_mgr, true);

			dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, true);

			clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;

		}
@@ -166,6 +167,7 @@ static void dcn31_update_clocks(struct clk_mgr *clk_mgr_base, 
		if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW &&

				new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {

			dcn31_smu_set_Z9_support(clk_mgr, false);

			dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, false);

			clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;

		}

drivers/gpu/drm/amd/display/dc/core/dc.c

+1 −1
Original line number Diff line number Diff line
@@ -1562,7 +1562,7 @@ static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context) 
}



#if defined(CONFIG_DRM_AMD_DC_DCN)

void dc_z10_restore(struct dc *dc)

void dc_z10_restore(const struct dc *dc)

{

	if (dc->hwss.z10_restore)

		dc->hwss.z10_restore(dc);

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+4 −0
Original line number Diff line number Diff line
@@ -1250,6 +1250,10 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason) 
		}

	}



#if defined(CONFIG_DRM_AMD_DC_DCN)

	dc_z10_restore(dc);

#endif



	/* get out of low power state */

	if (!can_apply_seamless_boot && reason != DETECT_REASON_BOOT)

		clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);

drivers/gpu/drm/amd/display/dc/dc.h

+1 −1
Original line number Diff line number Diff line
@@ -1363,7 +1363,7 @@ void dc_hardware_release(struct dc *dc); 


bool dc_set_psr_allow_active(struct dc *dc, bool enable);

#if defined(CONFIG_DRM_AMD_DC_DCN)

void dc_z10_restore(struct dc *dc);

void dc_z10_restore(const struct dc *dc);

void dc_z10_save_init(struct dc *dc);

#endif