Commit abf0878c authored by Nicholas Piggin's avatar Nicholas Piggin Committed by Michael Ellerman
Browse files

powerpc/64s: POWER10 nest MMU does not require flush escalation workaround 



Per (non-public) Nest MMU Workbook, POWER10 and POWER9P NMMU does not
cache PTEs in PWC, so does not require PWC flush to invalidate these
translations.

Skip the workaround on POWER10 and later.

Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220525022358.780745-2-npiggin@gmail.com
parent ef1911c6

arch/powerpc/mm/book3s64/radix_tlb.c

+11 −3
Original line number Diff line number Diff line
@@ -755,10 +755,18 @@ EXPORT_SYMBOL(radix__local_flush_tlb_page); 
static bool mm_needs_flush_escalation(struct mm_struct *mm)

{

	/*

	 * P9 nest MMU has issues with the page walk cache

	 * caching PTEs and not flushing them properly when

	 * RIC = 0 for a PID/LPID invalidate

	 * The P9 nest MMU has issues with the page walk cache caching PTEs

	 * and not flushing them when RIC = 0 for a PID/LPID invalidate.

	 *

	 * This may have been fixed in shipping firmware (by disabling PWC

	 * or preventing it from caching PTEs), but until that is confirmed,

	 * this workaround is required - escalate all RIC=0 IS=1/2/3 flushes

	 * to RIC=2.

	 *

	 * POWER10 (and P9P) does not have this problem.

	 */

	if (cpu_has_feature(CPU_FTR_ARCH_31))

		return false;

	if (atomic_read(&mm->context.copros) > 0)

		return true;

	return false;