Commit abd873af authored by Icenowy Zheng's avatar Icenowy Zheng Committed by Daniel Lezcano
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dt-bindings: timer: sifive,clint: add comaptibles for T-Head's C9xx 



T-Head C906/C910 CLINT is not compliant to SiFive ones (and even not
compliant to the newcoming ACLINT spec) because of lack of mtime
register.

Add a compatible string formatted like the C9xx-specific PLIC
compatible, and do not allow a SiFive one as fallback because they're
not really compliant.

Signed-off-by: default avatarIcenowy Zheng <uwu@icenowy.me>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarSamuel Holland <samuel@sholland.org>
Acked-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230202072814.319903-1-uwu@icenowy.me


Signed-off-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
parent 27788e01

Documentation/devicetree/bindings/timer/sifive,clint.yaml

+8 −0
Original line number Diff line number Diff line
@@ -20,6 +20,10 @@ description: 
  property of "/cpus" DT node. The "timebase-frequency" DT property is

  described in Documentation/devicetree/bindings/riscv/cpus.yaml



  T-Head C906/C910 CPU cores include an implementation of CLINT too, however

  their implementation lacks a memory-mapped MTIME register, thus not

  compatible with SiFive ones.



properties:

  compatible:

    oneOf:
@@ -29,6 +33,10 @@ properties: 
              - starfive,jh7100-clint

              - canaan,k210-clint

          - const: sifive,clint0

      - items:

          - enum:

              - allwinner,sun20i-d1-clint

          - const: thead,c900-clint

      - items:

          - const: sifive,clint0

          - const: riscv,clint0