Commit abc17128 authored by Catalin Marinas's avatar Catalin Marinas
Browse files

Merge branch 'for-next/feat_s1pie' into for-next/core 

* for-next/feat_s1pie:
  : Support for the Armv8.9 Permission Indirection Extensions (stage 1 only)
  KVM: selftests: get-reg-list: add Permission Indirection registers
  KVM: selftests: get-reg-list: support ID register features
  arm64: Document boot requirements for PIE
  arm64: transfer permission indirection settings to EL2
  arm64: enable Permission Indirection Extension (PIE)
  arm64: add encodings of PIRx_ELx registers
  arm64: disable EL2 traps for PIE
  arm64: reorganise PAGE_/PROT_ macros
  arm64: add PTE_WRITE to PROT_SECT_NORMAL
  arm64: add PTE_UXN/PTE_WRITE to SWAPPER_*_FLAGS
  KVM: arm64: expose ID_AA64MMFR3_EL1 to guests
  KVM: arm64: Save/restore PIE registers
  KVM: arm64: Save/restore TCR2_EL1
  arm64: cpufeature: add Permission Indirection Extension cpucap
  arm64: cpufeature: add TCR2 cpucap
  arm64: cpufeature: add system register ID_AA64MMFR3
  arm64/sysreg: add PIR*_ELx registers
  arm64/sysreg: update HCRX_EL2 register
  arm64/sysreg: add system registers TCR2_ELx
  arm64/sysreg: Add ID register ID_AA64MMFR3
parents f42039d1 5f0419a0

Documentation/arm64/booting.rst

+26 −0
Original line number Diff line number Diff line
@@ -385,6 +385,32 @@ Before jumping into the kernel, the following conditions must be met: 


    - HCRX_EL2.MSCEn (bit 11) must be initialised to 0b1.



  For CPUs with the Extended Translation Control Register feature (FEAT_TCR2):



  - If EL3 is present:



    - SCR_EL3.TCR2En (bit 43) must be initialised to 0b1.



 - If the kernel is entered at EL1 and EL2 is present:



    - HCRX_EL2.TCR2En (bit 14) must be initialised to 0b1.



  For CPUs with the Stage 1 Permission Indirection Extension feature (FEAT_S1PIE):



  - If EL3 is present:



    - SCR_EL3.PIEn (bit 45) must be initialised to 0b1.



  - If the kernel is entered at EL1 and EL2 is present:



    - HFGRTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.



    - HFGWTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.



    - HFGRTR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.



    - HFGRWR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.



The requirements described above for CPU mode, caches, MMUs, architected

timers, coherency and system registers apply to all CPUs.  All CPUs must

enter the kernel in the same exception level.  Where the values documented

arch/arm64/include/asm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -56,6 +56,7 @@ struct cpuinfo_arm64 { 
	u64		reg_id_aa64mmfr0;

	u64		reg_id_aa64mmfr1;

	u64		reg_id_aa64mmfr2;

	u64		reg_id_aa64mmfr3;

	u64		reg_id_aa64pfr0;

	u64		reg_id_aa64pfr1;

	u64		reg_id_aa64zfr0;

arch/arm64/include/asm/el2_setup.h

+10 −1
Original line number Diff line number Diff line
@@ -159,12 +159,21 @@ 
	mov	x0, xzr

	mrs	x1, id_aa64pfr1_el1

	ubfx	x1, x1, #ID_AA64PFR1_EL1_SME_SHIFT, #4

	cbz	x1, .Lset_fgt_\@

	cbz	x1, .Lset_pie_fgt_\@



	/* Disable nVHE traps of TPIDR2 and SMPRI */

	orr	x0, x0, #HFGxTR_EL2_nSMPRI_EL1_MASK

	orr	x0, x0, #HFGxTR_EL2_nTPIDR2_EL0_MASK



.Lset_pie_fgt_\@:

	mrs_s	x1, SYS_ID_AA64MMFR3_EL1

	ubfx	x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4

	cbz	x1, .Lset_fgt_\@



	/* Disable trapping of PIR_EL1 / PIRE0_EL1 */

	orr	x0, x0, #HFGxTR_EL2_nPIR_EL1

	orr	x0, x0, #HFGxTR_EL2_nPIRE0_EL1



.Lset_fgt_\@:

	msr_s	SYS_HFGRTR_EL2, x0

	msr_s	SYS_HFGWTR_EL2, x0

arch/arm64/include/asm/kernel-pgtable.h

+4 −4
Original line number Diff line number Diff line
@@ -107,14 +107,14 @@ 
/*

 * Initial memory map attributes.

 */

#define SWAPPER_PTE_FLAGS	(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)

#define SWAPPER_PMD_FLAGS	(PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)

#define SWAPPER_PTE_FLAGS	(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED | PTE_UXN)

#define SWAPPER_PMD_FLAGS	(PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S | PTE_UXN)



#ifdef CONFIG_ARM64_4K_PAGES

#define SWAPPER_RW_MMUFLAGS	(PMD_ATTRINDX(MT_NORMAL) | SWAPPER_PMD_FLAGS)

#define SWAPPER_RW_MMUFLAGS	(PMD_ATTRINDX(MT_NORMAL) | SWAPPER_PMD_FLAGS | PTE_WRITE)

#define SWAPPER_RX_MMUFLAGS	(SWAPPER_RW_MMUFLAGS | PMD_SECT_RDONLY)

#else

#define SWAPPER_RW_MMUFLAGS	(PTE_ATTRINDX(MT_NORMAL) | SWAPPER_PTE_FLAGS)

#define SWAPPER_RW_MMUFLAGS	(PTE_ATTRINDX(MT_NORMAL) | SWAPPER_PTE_FLAGS | PTE_WRITE)

#define SWAPPER_RX_MMUFLAGS	(SWAPPER_RW_MMUFLAGS | PTE_RDONLY)

#endif

arch/arm64/include/asm/kvm_arm.h

+2 −2
Original line number Diff line number Diff line
@@ -93,8 +93,8 @@ 
#define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC)

#define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)



#define HCRX_GUEST_FLAGS (HCRX_EL2_SMPME)

#define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn)

#define HCRX_GUEST_FLAGS (HCRX_EL2_SMPME | HCRX_EL2_TCR2En)

#define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En)



/* TCR_EL2 Registers bits */

#define TCR_EL2_RES1		((1U << 31) | (1 << 23))