Commit aba3c3fe authored by Shen, George's avatar Shen, George Committed by Alex Deucher
Browse files

drm/amd/display: Clear DPCD lane settings after repeater training 



[Why]
VS and PE requested by repeater should not persist for the sink.

[How]
Clear DPCD lane settings after repeater link training finishes.

Reviewed-by: default avatarWesley Chalmers <wesley.chalmers@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarGeorge Shen <George.Shen@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9311ed1e

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+1 −1
Original line number Diff line number Diff line
@@ -2138,7 +2138,7 @@ static enum link_training_result dp_perform_8b_10b_link_training( 
		}



		for (lane = 0; lane < (uint8_t)lt_settings->link_settings.lane_count; lane++)

			lt_settings->dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET = VOLTAGE_SWING_LEVEL0;

			lt_settings->dpcd_lane_settings[lane].raw = 0;

	}



	if (status == LINK_TRAINING_SUCCESS) {