Commit ab5d964c authored by Matthew Auld's avatar Matthew Auld
Browse files

drm/i915/selftests: mark up hugepages object with start_cpu_write 



Just like we do for internal objects. Also just use
i915_gem_object_set_cache_coherency() here. No need for over-flushing on
LLC platforms.

Signed-off-by: default avatarMatthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: default avatarThomas Hellström <thomas.hellstrom@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211018174508.2137279-9-matthew.auld@intel.com
parent 3884d8af

drivers/gpu/drm/i915/gem/selftests/huge_pages.c

+6 −1
Original line number Diff line number Diff line
@@ -136,6 +136,8 @@ static void put_huge_pages(struct drm_i915_gem_object *obj, 
	huge_pages_free_pages(pages);



	obj->mm.dirty = false;



	__start_cpu_write(obj);

}



static const struct drm_i915_gem_object_ops huge_page_ops = {
@@ -152,6 +154,7 @@ huge_pages_object(struct drm_i915_private *i915, 
{

	static struct lock_class_key lock_class;

	struct drm_i915_gem_object *obj;

	unsigned int cache_level;



	GEM_BUG_ON(!size);

	GEM_BUG_ON(!IS_ALIGNED(size, BIT(__ffs(page_mask))));
@@ -173,7 +176,9 @@ huge_pages_object(struct drm_i915_private *i915, 


	obj->write_domain = I915_GEM_DOMAIN_CPU;

	obj->read_domains = I915_GEM_DOMAIN_CPU;

	obj->cache_level = I915_CACHE_NONE;



	cache_level = HAS_LLC(i915) ? I915_CACHE_LLC : I915_CACHE_NONE;

	i915_gem_object_set_cache_coherency(obj, cache_level);



	obj->mm.page_mask = page_mask;