Commit ab597bb3 authored by José Roberto de Souza's avatar José Roberto de Souza
Browse files

drm/i915/display: Group PSR2 prog sequences and workarounds 



Grouping inside of the same if all the programing sequences and
workarounds of PSR2.
The order of programing changed in intel_psr_enable_source() but
it will not affect PSR2 as at this point PSR2_ENABLE is still disabled.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Reviewed-by: default avatarJouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220210185223.95399-1-jose.souza@intel.com
parent b70ad01a

drivers/gpu/drm/i915/display/intel_psr.c

+37 −40
Original line number Diff line number Diff line
@@ -1069,25 +1069,6 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp) 
	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

	u32 mask;



	if (intel_dp->psr.psr2_enabled && DISPLAY_VER(dev_priv) == 9) {

		i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);

		u32 chicken = intel_de_read(dev_priv, reg);



		chicken |= PSR2_VSC_ENABLE_PROG_HEADER |

			   PSR2_ADD_VERTICAL_LINE_COUNT;

		intel_de_write(dev_priv, reg, chicken);

	}



	/*

	 * Wa_16014451276:adlp

	 * All supported adlp panels have 1-based X granularity, this may

	 * cause issues if non-supported panels are used.

	 */

	if (IS_ALDERLAKE_P(dev_priv) &&

	    intel_dp->psr.psr2_enabled)

		intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,

			     ADLP_1_BASED_X_GRANULARITY);



	/*

	 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also

	 * mask LPSP to avoid dependency on other drivers that might block
@@ -1126,19 +1107,34 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp) 
			     intel_dp->psr.psr2_sel_fetch_enabled ?

			     IGNORE_PSR2_HW_TRACKING : 0);



	if (intel_dp->psr.psr2_enabled) {

		if (DISPLAY_VER(dev_priv) == 9)

			intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,

				     PSR2_VSC_ENABLE_PROG_HEADER |

				     PSR2_ADD_VERTICAL_LINE_COUNT);



		/*

		 * Wa_16014451276:adlp

		 * All supported adlp panels have 1-based X granularity, this may

		 * cause issues if non-supported panels are used.

		 */

		if (IS_ALDERLAKE_P(dev_priv))

			intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,

				     ADLP_1_BASED_X_GRANULARITY);



		/* Wa_16011168373:adl-p */

	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) &&

	    intel_dp->psr.psr2_enabled)

		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))

			intel_de_rmw(dev_priv,

				     TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),

				     TRANS_SET_CONTEXT_LATENCY_MASK,

				     TRANS_SET_CONTEXT_LATENCY_VALUE(1));



		/* Wa_16012604467:adlp */

	if (IS_ALDERLAKE_P(dev_priv) && intel_dp->psr.psr2_enabled)

		if (IS_ALDERLAKE_P(dev_priv))

			intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0,

				     CLKGATE_DIS_MISC_DMASC_GATING_DIS);

	}

}



static bool psr_interrupt_error_check(struct intel_dp *intel_dp)

{
@@ -1290,17 +1286,18 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) 
		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,

			     DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);



	if (intel_dp->psr.psr2_enabled) {

		/* Wa_16011168373:adl-p */

	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) &&

	    intel_dp->psr.psr2_enabled)

		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))

			intel_de_rmw(dev_priv,

				     TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),

				     TRANS_SET_CONTEXT_LATENCY_MASK, 0);



		/* Wa_16012604467:adlp */

	if (IS_ALDERLAKE_P(dev_priv) && intel_dp->psr.psr2_enabled)

		if (IS_ALDERLAKE_P(dev_priv))

			intel_de_rmw(dev_priv, CLKGATE_DIS_MISC,

				     CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0);

	}



	intel_snps_phy_update_psr_power_state(dev_priv, phy, false);