Commit ab52be1b authored Jan 07, 2023 by Sean Christopherson

KVM: x86: Inject #GP on x2APIC WRMSR that sets reserved bits 63:32



Reject attempts to set bits 63:32 for 32-bit x2APIC registers, i.e. all
x2APIC registers except ICR.  Per Intel's SDM:

  Non-zero writes (by WRMSR instruction) to reserved bits to these
  registers will raise a general protection fault exception

Opportunistically fix a typo in a nearby comment.

Reported-by: Marc Orr <marcorr@google.com>
Cc: stable@vger.kernel.org
Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
Link: https://lore.kernel.org/r/20230107011025.565472-3-seanjc@google.com


Signed-off-by: Sean Christopherson <seanjc@google.com>

parent ba5838ab

arch/x86/kvm/lapic.c

+5 −1

Original line number	Diff line number	Diff line
		@@ -3114,13 +3114,17 @@ static int kvm_lapic_msr_read(struct kvm_lapic apic, u32 reg, u64 data)
		static int kvm_lapic_msr_write(struct kvm_lapic *apic, u32 reg, u64 data)
		{
		/*
		* ICR is a 64-bit register in x2APIC mode (and Hyper'v PV vAPIC) and
		* ICR is a 64-bit register in x2APIC mode (and Hyper-V PV vAPIC) and
		* can be written as such, all other registers remain accessible only
		* through 32-bit reads/writes.
		*/
		if (reg == APIC_ICR)
		return kvm_x2apic_icr_write(apic, data);

		/* Bits 63:32 are reserved in all other registers. */
		if (data >> 32)
		return 1;

		return kvm_lapic_reg_write(apic, reg, (u32)data);
		}