Unverified Commit ab45699e authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!7577 spi: hisi-kunpeng：backport some bugfixes 

Merge Pull Request from: @barbo 
 
from upstream:
9f589046 spi: hisi-kunpeng: switch to use modern name
120e1aa2 spi: hisi-kunpeng: Fix error checking

from OLK-6.6(Devyn Liu):
51291a22 spi: hisi-kunpeng: Add validation for the minimum value of speed_hz
8c9aeaf8 spi: Add verification for the max_frequency provided by the firmware

issue：[I9QOAJ](https://gitee.com/openeuler/kernel/issues/I9QOAJ) 
 
Link:https://gitee.com/openeuler/kernel/pulls/7577

 

Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents fc0744ef ebb5c34d

drivers/spi/spi-hisi-kunpeng.c

+50 −43
Original line number Diff line number Diff line
@@ -162,12 +162,12 @@ static int hisi_spi_debugfs_init(struct hisi_spi *hs) 
{

	char name[32];



	struct spi_controller *master;

	struct spi_controller *host;



	master = container_of(hs->dev, struct spi_controller, dev);

	snprintf(name, 32, "hisi_spi%d", master->bus_num);

	host = container_of(hs->dev, struct spi_controller, dev);

	snprintf(name, 32, "hisi_spi%d", host->bus_num);

	hs->debugfs = debugfs_create_dir(name, NULL);

	if (!hs->debugfs)

	if (IS_ERR(hs->debugfs))

		return -ENOMEM;



	hs->regset.regs = hisi_spi_regs;
@@ -289,18 +289,18 @@ static void __hisi_calc_div_reg(struct hisi_chip_data *chip) 
	chip->div_post = (chip->clk_div / chip->div_pre) - 1;

}



static u32 hisi_calc_effective_speed(struct spi_controller *master,

static u32 hisi_calc_effective_speed(struct spi_controller *host,

			struct hisi_chip_data *chip, u32 speed_hz)

{

	u32 effective_speed;



	/* Note clock divider doesn't support odd numbers */

	chip->clk_div = DIV_ROUND_UP(master->max_speed_hz, speed_hz) + 1;

	chip->clk_div = DIV_ROUND_UP(host->max_speed_hz, speed_hz) + 1;

	chip->clk_div &= 0xfffe;

	if (chip->clk_div > CLK_DIV_MAX)

		chip->clk_div = CLK_DIV_MAX;



	effective_speed = master->max_speed_hz / chip->clk_div;

	effective_speed = host->max_speed_hz / chip->clk_div;

	if (chip->speed_hz != effective_speed) {

		__hisi_calc_div_reg(chip);

		chip->speed_hz = effective_speed;
@@ -334,20 +334,20 @@ static void hisi_spi_hw_init(struct hisi_spi *hs) 


static irqreturn_t hisi_spi_irq(int irq, void *dev_id)

{

	struct spi_controller *master = dev_id;

	struct hisi_spi *hs = spi_controller_get_devdata(master);

	struct spi_controller *host = dev_id;

	struct hisi_spi *hs = spi_controller_get_devdata(host);

	u32 irq_status = readl(hs->regs + HISI_SPI_ISR) & ISR_MASK;



	if (!irq_status)

		return IRQ_NONE;



	if (!master->cur_msg)

	if (!host->cur_msg)

		return IRQ_HANDLED;



	/* Error handling */

	if (irq_status & ISR_RXOF) {

		dev_err(hs->dev, "interrupt_transfer: fifo overflow\n");

		master->cur_msg->status = -EIO;

		host->cur_msg->status = -EIO;

		goto finalize_transfer;

	}
@@ -367,20 +367,20 @@ static irqreturn_t hisi_spi_irq(int irq, void *dev_id) 


finalize_transfer:

	hisi_spi_disable(hs);

	spi_finalize_current_transfer(master);

	spi_finalize_current_transfer(host);

	return IRQ_HANDLED;

}



static int hisi_spi_transfer_one(struct spi_controller *master,

static int hisi_spi_transfer_one(struct spi_controller *host,

		struct spi_device *spi, struct spi_transfer *transfer)

{

	struct hisi_spi *hs = spi_controller_get_devdata(master);

	struct hisi_spi *hs = spi_controller_get_devdata(host);

	struct hisi_chip_data *chip = spi_get_ctldata(spi);

	u32 cr = chip->cr;



	/* Update per transfer options for speed and bpw */

	transfer->effective_speed_hz =

		hisi_calc_effective_speed(master, chip, transfer->speed_hz);

		hisi_calc_effective_speed(host, chip, transfer->speed_hz);

	cr |= FIELD_PREP(CR_DIV_PRE_MASK, chip->div_pre);

	cr |= FIELD_PREP(CR_DIV_POST_MASK, chip->div_post);

	cr |= FIELD_PREP(CR_BPW_MASK, transfer->bits_per_word - 1);
@@ -407,10 +407,10 @@ static int hisi_spi_transfer_one(struct spi_controller *master, 
	return 1;

}



static void hisi_spi_handle_err(struct spi_controller *master,

static void hisi_spi_handle_err(struct spi_controller *host,

		struct spi_message *msg)

{

	struct hisi_spi *hs = spi_controller_get_devdata(master);

	struct hisi_spi *hs = spi_controller_get_devdata(host);



	hisi_spi_disable(hs);
@@ -450,7 +450,7 @@ static void hisi_spi_cleanup(struct spi_device *spi) 
static int hisi_spi_probe(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;

	struct spi_controller *master;

	struct spi_controller *host;

	struct hisi_spi *hs;

	int ret, irq;
@@ -458,13 +458,13 @@ static int hisi_spi_probe(struct platform_device *pdev) 
	if (irq < 0)

		return irq;



	master = devm_spi_alloc_master(dev, sizeof(*hs));

	if (!master)

	host = devm_spi_alloc_master(dev, sizeof(*hs));

	if (!host)

		return -ENOMEM;



	platform_set_drvdata(pdev, master);

	platform_set_drvdata(pdev, host);



	hs = spi_controller_get_devdata(master);

	hs = spi_controller_get_devdata(host);

	hs->dev = dev;

	hs->irq = irq;
@@ -472,42 +472,49 @@ static int hisi_spi_probe(struct platform_device *pdev) 
	if (IS_ERR(hs->regs))

		return PTR_ERR(hs->regs);



	/* Specify maximum SPI clocking speed (master only) by firmware */

	/* Specify maximum SPI clocking speed (host only) by firmware */

	ret = device_property_read_u32(dev, "spi-max-frequency",

					&master->max_speed_hz);

					&host->max_speed_hz);

	if (ret) {

		dev_err(dev, "failed to get max SPI clocking speed, ret=%d\n",

			ret);

		return -EINVAL;

	}



	if (host->max_speed_hz == 0) {

		dev_err(dev, "invalid max SPI clocking speed, max-freq=%u\n",

				host->max_speed_hz);

		return -EINVAL;

	}



	ret = device_property_read_u16(dev, "num-cs",

					&master->num_chipselect);

					&host->num_chipselect);

	if (ret)

		master->num_chipselect = DEFAULT_NUM_CS;



	master->use_gpio_descriptors = true;

	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;

	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);

	master->bus_num = pdev->id;

	master->setup = hisi_spi_setup;

	master->cleanup = hisi_spi_cleanup;

	master->transfer_one = hisi_spi_transfer_one;

	master->handle_err = hisi_spi_handle_err;

	master->dev.fwnode = dev->fwnode;

		host->num_chipselect = DEFAULT_NUM_CS;



	host->use_gpio_descriptors = true;

	host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;

	host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);

	host->bus_num = pdev->id;

	host->setup = hisi_spi_setup;

	host->cleanup = hisi_spi_cleanup;

	host->transfer_one = hisi_spi_transfer_one;

	host->handle_err = hisi_spi_handle_err;

	host->dev.fwnode = dev->fwnode;

	host->min_speed_hz = DIV_ROUND_UP(host->max_speed_hz, CLK_DIV_MAX);



	hisi_spi_hw_init(hs);



	ret = devm_request_irq(dev, hs->irq, hisi_spi_irq, 0, dev_name(dev),

			master);

			       host);

	if (ret < 0) {

		dev_err(dev, "failed to get IRQ=%d, ret=%d\n", hs->irq, ret);

		return ret;

	}



	ret = spi_register_controller(master);

	ret = spi_register_controller(host);

	if (ret) {

		dev_err(dev, "failed to register spi master, ret=%d\n", ret);

		dev_err(dev, "failed to register spi host, ret=%d\n", ret);

		return ret;

	}
@@ -516,18 +523,18 @@ static int hisi_spi_probe(struct platform_device *pdev) 


	dev_info(dev, "hw version:0x%x max-freq:%u kHz\n",

		readl(hs->regs + HISI_SPI_VERSION),

		master->max_speed_hz / 1000);

		host->max_speed_hz / 1000);



	return 0;

}



static int hisi_spi_remove(struct platform_device *pdev)

{

	struct spi_controller *master = platform_get_drvdata(pdev);

	struct hisi_spi *hs = spi_controller_get_devdata(master);

	struct spi_controller *host = platform_get_drvdata(pdev);

	struct hisi_spi *hs = spi_controller_get_devdata(host);



	debugfs_remove_recursive(hs->debugfs);

	spi_unregister_controller(master);

	spi_unregister_controller(host);



	return 0;

}