Commit ab3906c5 authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/errata' into for-next/core 

* for-next/errata: (3 commits)
  arm64: Workaround for Cortex-A55 erratum 1530923
  ...
parents aa246c05 275fa0ea

Documentation/arm64/silicon-errata.rst

+2 −0
Original line number Diff line number Diff line
@@ -88,6 +88,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A76      | #1463225        | ARM64_ERRATUM_1463225       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A55      | #1530923        | ARM64_ERRATUM_1530923       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1188873,1418040| ARM64_ERRATUM_1418040       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1349291        | N/A                         |

arch/arm64/Kconfig

+21 −0
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@@ -518,9 +518,13 @@ config ARM64_ERRATUM_1418040 


	  If unsure, say Y.



config ARM64_WORKAROUND_SPECULATIVE_AT_VHE

	bool



config ARM64_ERRATUM_1165522

	bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"

	default y

	select ARM64_WORKAROUND_SPECULATIVE_AT_VHE

	help

	  This option adds a workaround for ARM Cortex-A76 erratum 1165522.
@@ -530,6 +534,19 @@ config ARM64_ERRATUM_1165522 


	  If unsure, say Y.



config ARM64_ERRATUM_1530923

	bool "Cortex-A55: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"

	default y

	select ARM64_WORKAROUND_SPECULATIVE_AT_VHE

	help

	  This option adds a workaround for ARM Cortex-A55 erratum 1530923.



	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with

	  corrupted TLBs by speculating an AT instruction during a guest

	  context switch.



	  If unsure, say Y.



config ARM64_ERRATUM_1286807

	bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"

	default y
@@ -546,9 +563,13 @@ config ARM64_ERRATUM_1286807 
	  invalidated has been observed by other observers. The

	  workaround repeats the TLBI+DSB operation.



config ARM64_WORKAROUND_SPECULATIVE_AT_NVHE

	bool



config ARM64_ERRATUM_1319367

	bool "Cortex-A57/A72: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"

	default y

	select ARM64_WORKAROUND_SPECULATIVE_AT_NVHE

	help

	  This option adds work arounds for ARM Cortex-A57 erratum 1319537

	  and A72 erratum 1319367

arch/arm64/include/asm/cpucaps.h

+2 −2
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@@ -44,7 +44,7 @@ 
#define ARM64_SSBS				34

#define ARM64_WORKAROUND_1418040		35

#define ARM64_HAS_SB				36

#define ARM64_WORKAROUND_1165522		37

#define ARM64_WORKAROUND_SPECULATIVE_AT_VHE	37

#define ARM64_HAS_ADDRESS_AUTH_ARCH		38

#define ARM64_HAS_ADDRESS_AUTH_IMP_DEF		39

#define ARM64_HAS_GENERIC_AUTH_ARCH		40
@@ -55,7 +55,7 @@ 
#define ARM64_WORKAROUND_CAVIUM_TX2_219_TVM	45

#define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM	46

#define ARM64_WORKAROUND_1542419		47

#define ARM64_WORKAROUND_1319367		48

#define ARM64_WORKAROUND_SPECULATIVE_AT_NVHE	48

#define ARM64_HAS_E0PD				49



#define ARM64_NCAPS				50

arch/arm64/include/asm/kvm_host.h

+1 −1
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@@ -571,7 +571,7 @@ static inline bool kvm_arch_requires_vhe(void) 
		return true;



	/* Some implementations have defects that confine them to VHE */

	if (cpus_have_cap(ARM64_WORKAROUND_1165522))

	if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_AT_VHE))

		return true;



	return false;

arch/arm64/include/asm/kvm_hyp.h

+3 −3
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@@ -91,11 +91,11 @@ static __always_inline void __hyp_text __load_guest_stage2(struct kvm *kvm) 
	write_sysreg(kvm_get_vttbr(kvm), vttbr_el2);



	/*

	 * ARM erratum 1165522 requires the actual execution of the above

	 * before we can switch to the EL1/EL0 translation regime used by

	 * ARM errata 1165522 and 1530923 require the actual execution of the

	 * above before we can switch to the EL1/EL0 translation regime used by

	 * the guest.

	 */

	asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_1165522));

	asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT_VHE));

}



#endif /* __ARM64_KVM_HYP_H__ */