Unverified Commit ab2dbc7a authored Jul 11, 2023 by Palmer Dabbelt

RISC-V: Don't include Zicsr or Zifencei in I from ACPI



ACPI ISA strings are based on a specification after Zicsr and Zifencei
were split out of I, so we shouldn't be treating them as part of I.  We
haven't release an ACPI-based kernel yet, so we don't need to worry
about compatibility with the old ISA strings.

Fixes: 07edc327 ("RISC-V: always report presence of extensions formerly part of the base ISA")
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Link: https://lore.kernel.org/r/20230711224600.10879-1-palmer@rivosinc.com


Cc: stable@vger.kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

parent b690e266

arch/riscv/kernel/cpufeature.c

+2 −7

Original line number	Diff line number	Diff line
		@@ -317,19 +317,14 @@ void __init riscv_fill_hwcap(void)
		#undef SET_ISA_EXT_MAP
		}

		/*
		* Linux requires the following extensions, so we may as well
		* always set them.
		*/
		set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
		set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);

		/*
		* These ones were as they were part of the base ISA when the
		* port & dt-bindings were upstreamed, and so can be set
		* unconditionally where `i` is in riscv,isa on DT systems.
		*/
		if (acpi_disabled) {
		set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
		set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
		set_bit(RISCV_ISA_EXT_ZICNTR, isainfo->isa);
		set_bit(RISCV_ISA_EXT_ZIHPM, isainfo->isa);
		}