Commit ab2d78e6 authored by Kaustabh Chakraborty's avatar Kaustabh Chakraborty Committed by Wentao Guan
Browse files

phy: exynos5-usbdrd: fix MPLL_MULTIPLIER and SSC_REFCLKSEL masks in refclk

stable inclusion
from stable-v6.6.81
commit 4bddfde8b692d6e07021607236efbc2c2e9f0d0d
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/IBYZED

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=4bddfde8b692d6e07021607236efbc2c2e9f0d0d



--------------------------------

commit e2158c953c973adb49383ddea2504faf08d375b7 upstream.

In exynos5_usbdrd_{pipe3,utmi}_set_refclk(), the masks
PHYCLKRST_MPLL_MULTIPLIER_MASK and PHYCLKRST_SSC_REFCLKSEL_MASK are not
inverted when applied to the register values. Fix it.

Cc: stable@vger.kernel.org
Fixes: 59025887 ("phy: Add new Exynos5 USB 3.0 PHY driver")
Signed-off-by: default avatarKaustabh Chakraborty <kauschluss@disroot.org>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarAnand Moon <linux.amoon@gmail.com>
Link: https://lore.kernel.org/r/20250209-exynos5-usbdrd-masks-v1-1-4f7f83f323d7@disroot.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 4bddfde8b692d6e07021607236efbc2c2e9f0d0d)
Signed-off-by: default avatarWentao Guan <guanwentao@uniontech.com>
parent adf17455
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+6 −6
Original line number Diff line number Diff line
@@ -319,9 +319,9 @@ exynos5_usbdrd_pipe3_set_refclk(struct phy_usb_instance *inst)
	reg |=	PHYCLKRST_REFCLKSEL_EXT_REFCLK;

	/* FSEL settings corresponding to reference clock */
	reg &= ~PHYCLKRST_FSEL_PIPE_MASK |
	reg &= ~(PHYCLKRST_FSEL_PIPE_MASK |
		 PHYCLKRST_MPLL_MULTIPLIER_MASK |
		PHYCLKRST_SSC_REFCLKSEL_MASK;
		 PHYCLKRST_SSC_REFCLKSEL_MASK);
	switch (phy_drd->extrefclk) {
	case EXYNOS5_FSEL_50MHZ:
		reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF |
@@ -363,9 +363,9 @@ exynos5_usbdrd_utmi_set_refclk(struct phy_usb_instance *inst)
	reg &= ~PHYCLKRST_REFCLKSEL_MASK;
	reg |=	PHYCLKRST_REFCLKSEL_EXT_REFCLK;

	reg &= ~PHYCLKRST_FSEL_UTMI_MASK |
	reg &= ~(PHYCLKRST_FSEL_UTMI_MASK |
		 PHYCLKRST_MPLL_MULTIPLIER_MASK |
		PHYCLKRST_SSC_REFCLKSEL_MASK;
		 PHYCLKRST_SSC_REFCLKSEL_MASK);
	reg |= PHYCLKRST_FSEL(phy_drd->extrefclk);

	return reg;