Unverified Commit ab222a4a authored by Bard Liao's avatar Bard Liao Committed by Mark Brown
Browse files

ASoC: SOC: Intel: introduce cl_init callback 



The code loader init sequences are different between versions of
Intel platforms. Have a cl_init callback allows us to reuse the
common code.
No function changed.

Signed-off-by: default avatarBard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: default avatarPéter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: default avatarRander Wang <rander.wang@intel.com>
Reviewed-by: default avatarRanjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20220615084348.3489-2-yung-chuan.liao@linux.intel.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent d919630f

sound/soc/sof/intel/apl.c

+1 −0
Original line number Diff line number Diff line
@@ -101,6 +101,7 @@ const struct sof_intel_dsp_desc apl_chip_info = { 
	.ssp_base_offset = APL_SSP_BASE_OFFSET,

	.quirks = SOF_INTEL_PROCEN_FMT_QUIRK,

	.check_ipc_irq	= hda_dsp_check_ipc_irq,

	.cl_init = cl_dsp_init,

	.hw_ip_version = SOF_INTEL_CAVS_1_5_PLUS,

};

EXPORT_SYMBOL_NS(apl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);

sound/soc/sof/intel/cnl.c

+2 −0
Original line number Diff line number Diff line
@@ -401,6 +401,7 @@ const struct sof_intel_dsp_desc cnl_chip_info = { 
	.sdw_alh_base = SDW_ALH_BASE,

	.check_sdw_irq	= hda_common_check_sdw_irq,

	.check_ipc_irq	= hda_dsp_check_ipc_irq,

	.cl_init = cl_dsp_init,

	.hw_ip_version = SOF_INTEL_CAVS_1_8,

};

EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
@@ -430,6 +431,7 @@ const struct sof_intel_dsp_desc jsl_chip_info = { 
	.sdw_alh_base = SDW_ALH_BASE,

	.check_sdw_irq	= hda_common_check_sdw_irq,

	.check_ipc_irq	= hda_dsp_check_ipc_irq,

	.cl_init = cl_dsp_init,

	.hw_ip_version = SOF_INTEL_CAVS_2_0,

};

EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);

sound/soc/sof/intel/hda-loader.c

+12 −3
Original line number Diff line number Diff line
@@ -99,7 +99,7 @@ struct hdac_ext_stream *hda_cl_stream_prepare(struct snd_sof_dev *sdev, unsigned 
 * power on all host managed cores and only unstall/run the boot core to boot the

 * DSP then turn off all non boot cores (if any) is powered on.

 */

static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot)

int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot)

{

	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;

	const struct sof_intel_dsp_desc *chip = hda->desc;
@@ -369,9 +369,15 @@ int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev) 


static int hda_dsp_boot_imr(struct snd_sof_dev *sdev)

{

	const struct sof_intel_dsp_desc *chip_info;

	int ret;



	ret = cl_dsp_init(sdev, 0, true);

	chip_info = get_chip_info(sdev->pdata);

	if (chip_info->cl_init)

		ret = chip_info->cl_init(sdev, 0, true);

	else

		ret = -EINVAL;



	if (!ret)

		hda_sdw_process_wakeen(sdev);
@@ -430,7 +436,10 @@ int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev) 
			"Attempting iteration %d of Core En/ROM load...\n", i);



		hda->boot_iteration = i + 1;

		ret = cl_dsp_init(sdev, hext_stream->hstream.stream_tag, false);

		if (chip_info->cl_init)

			ret = chip_info->cl_init(sdev, hext_stream->hstream.stream_tag, false);

		else

			ret = -EINVAL;



		/* don't retry anymore if successful */

		if (!ret)

sound/soc/sof/intel/hda.h

+1 −0
Original line number Diff line number Diff line
@@ -602,6 +602,7 @@ struct hdac_ext_stream *hda_cl_stream_prepare(struct snd_sof_dev *sdev, unsigned 
					      int direction);

int hda_cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,

		   struct hdac_ext_stream *hext_stream);

int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot);

#define HDA_CL_STREAM_FORMAT 0x40



/* pre and post fw run ops */

sound/soc/sof/intel/icl.c

+1 −0
Original line number Diff line number Diff line
@@ -152,6 +152,7 @@ const struct sof_intel_dsp_desc icl_chip_info = { 
	.sdw_alh_base = SDW_ALH_BASE,

	.check_sdw_irq	= hda_common_check_sdw_irq,

	.check_ipc_irq	= hda_dsp_check_ipc_irq,

	.cl_init = cl_dsp_init,

	.hw_ip_version = SOF_INTEL_CAVS_2_0,

};

EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);