Commit aafe8853 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'hns3-next'



Huazhong Tan says:

====================
net: hns3: updates for -next

There are some updates for the HNS3 ethernet driver.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 77d0cab9 c155e22b
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+4 −2
Original line number Diff line number Diff line
@@ -42,8 +42,9 @@
#define HNAE3_DEV_ID_50GE_RDMA			0xA224
#define HNAE3_DEV_ID_50GE_RDMA_MACSEC		0xA225
#define HNAE3_DEV_ID_100G_RDMA_MACSEC		0xA226
#define HNAE3_DEV_ID_100G_VF			0xA22E
#define HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF	0xA22F
#define HNAE3_DEV_ID_200G_RDMA			0xA228
#define HNAE3_DEV_ID_VF				0xA22E
#define HNAE3_DEV_ID_RDMA_DCB_PFC_VF		0xA22F

#define HNAE3_CLASS_NAME_SIZE 16

@@ -152,6 +153,7 @@ enum hnae3_hw_error_type {
	HNAE3_PPU_POISON_ERROR,
	HNAE3_CMDQ_ECC_ERROR,
	HNAE3_IMP_RD_POISON_ERROR,
	HNAE3_ROCEE_AXI_RESP_ERROR,
};

enum hnae3_reset_type {
+2 −1
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ static int hns3_dbg_queue_info(struct hnae3_handle *h,
	struct hns3_enet_ring *ring;
	u32 base_add_l, base_add_h;
	u32 queue_num, queue_max;
	u32 value, i = 0;
	u32 value, i;
	int cnt;

	if (!priv->ring) {
@@ -264,6 +264,7 @@ static void hns3_dbg_help(struct hnae3_handle *h)
	dev_info(&h->pdev->dev, "dump qs shaper [qs id]\n");
	dev_info(&h->pdev->dev, "dump uc mac list <func id>\n");
	dev_info(&h->pdev->dev, "dump mc mac list <func id>\n");
	dev_info(&h->pdev->dev, "dump intr\n");

	memset(printf_buf, 0, HNS3_DBG_BUF_LEN);
	strncat(printf_buf, "dump reg [[bios common] [ssu <port_id>]",
+11 −6
Original line number Diff line number Diff line
@@ -81,8 +81,10 @@ static const struct pci_device_id hns3_pci_tbl[] = {
	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA),
	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},
	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
	/* required last entry */
	{0, }
@@ -1254,7 +1256,7 @@ static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,

void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
{
	int i = 0;
	int i;

	for (i = 0; i < MAX_SKB_FRAGS; i++)
		size[i] = skb_frag_size(&shinfo->frags[i]);
@@ -2044,9 +2046,10 @@ bool hns3_is_phys_func(struct pci_dev *pdev)
	case HNAE3_DEV_ID_50GE_RDMA:
	case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
	case HNAE3_DEV_ID_100G_RDMA_MACSEC:
	case HNAE3_DEV_ID_200G_RDMA:
		return true;
	case HNAE3_DEV_ID_100G_VF:
	case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
	case HNAE3_DEV_ID_VF:
	case HNAE3_DEV_ID_RDMA_DCB_PFC_VF:
		return false;
	default:
		dev_warn(&pdev->dev, "un-recognized pci device-id %u",
@@ -3511,7 +3514,7 @@ static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
	struct hnae3_ring_chain_node vector_ring_chain;
	struct hnae3_handle *h = priv->ae_handle;
	struct hns3_enet_tqp_vector *tqp_vector;
	int ret = 0;
	int ret;
	int i;

	hns3_nic_set_cpumask(priv);
@@ -4600,6 +4603,8 @@ static const struct hns3_hw_error_info hns3_hw_err[] = {
	  .msg = "IMP CMDQ error" },
	{ .type = HNAE3_IMP_RD_POISON_ERROR,
	  .msg = "IMP RD poison" },
	{ .type = HNAE3_ROCEE_AXI_RESP_ERROR,
	  .msg = "ROCEE AXI RESP error" },
};

static void hns3_process_hw_error(struct hnae3_handle *handle,
+1 −1
Original line number Diff line number Diff line
@@ -261,7 +261,7 @@ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num)
	bool complete = false;
	u32 timeout = 0;
	int handle = 0;
	int retval = 0;
	int retval;
	int ntc;

	spin_lock_bh(&hw->cmq.csq.lock);
+2 −0
Original line number Diff line number Diff line
@@ -491,6 +491,8 @@ struct hclge_pf_res_cmd {
#define HCLGE_CFG_RSS_SIZE_M	GENMASK(31, 24)
#define HCLGE_CFG_SPEED_ABILITY_S	0
#define HCLGE_CFG_SPEED_ABILITY_M	GENMASK(7, 0)
#define HCLGE_CFG_SPEED_ABILITY_EXT_S	10
#define HCLGE_CFG_SPEED_ABILITY_EXT_M	GENMASK(15, 10)
#define HCLGE_CFG_UMV_TBL_SPACE_S	16
#define HCLGE_CFG_UMV_TBL_SPACE_M	GENMASK(31, 16)

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