Commit aad611a8 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'perf-tools-fixes-for-v5.17-2022-03-12' of... 

Merge tag 'perf-tools-fixes-for-v5.17-2022-03-12' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux

Pull perf tools fixes from Arnaldo Carvalho de Melo:

 - Fix event parser error for hybrid systems

 - Fix NULL check against wrong variable in 'perf bench' and in the
   parsing code

 - Update arm64 KVM headers from the kernel sources

 - Sync cpufeatures header with the kernel sources

* tag 'perf-tools-fixes-for-v5.17-2022-03-12' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux:
  perf parse: Fix event parser error for hybrid systems
  perf bench: Fix NULL check against wrong variable
  perf parse-events: Fix NULL check against wrong variable
  tools headers cpufeatures: Sync with the kernel sources
  tools kvm headers arm64: Update KVM headers from the kernel sources
parents 1518a4f6 91c9923a

tools/arch/arm64/include/uapi/asm/kvm.h

+5 −0
Original line number Diff line number Diff line
@@ -281,6 +281,11 @@ struct kvm_arm_copy_mte_tags { 
#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED	3

#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED     	(1U << 4)



#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3	KVM_REG_ARM_FW_REG(3)

#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_AVAIL		0

#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_AVAIL		1

#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_REQUIRED	2



/* SVE registers */

#define KVM_REG_ARM64_SVE		(0x15 << KVM_REG_ARM_COPROC_SHIFT)

tools/arch/x86/include/asm/cpufeatures.h

+1 −1
Original line number Diff line number Diff line
@@ -204,7 +204,7 @@ 
/* FREE!                                ( 7*32+10) */

#define X86_FEATURE_PTI			( 7*32+11) /* Kernel Page Table Isolation enabled */

#define X86_FEATURE_RETPOLINE		( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */

#define X86_FEATURE_RETPOLINE_LFENCE	( 7*32+13) /* "" Use LFENCEs for Spectre variant 2 */

#define X86_FEATURE_RETPOLINE_LFENCE	( 7*32+13) /* "" Use LFENCE for Spectre variant 2 */

#define X86_FEATURE_INTEL_PPIN		( 7*32+14) /* Intel Processor Inventory Number */

#define X86_FEATURE_CDP_L2		( 7*32+15) /* Code and Data Prioritization L2 */

#define X86_FEATURE_MSR_SPEC_CTRL	( 7*32+16) /* "" MSR SPEC_CTRL is implemented */

tools/perf/bench/epoll-ctl.c

+1 −1
Original line number Diff line number Diff line
@@ -106,7 +106,7 @@ static void nest_epollfd(void) 
	printinfo("Nesting level(s): %d\n", nested);



	epollfdp = calloc(nested, sizeof(int));

	if (!epollfd)

	if (!epollfdp)

		err(EXIT_FAILURE, "calloc");



	for (i = 0; i < nested; i++) {

tools/perf/util/parse-events.c

+5 −3
Original line number Diff line number Diff line
@@ -1648,6 +1648,7 @@ int parse_events_multi_pmu_add(struct parse_events_state *parse_state, 
{

	struct parse_events_term *term;

	struct list_head *list = NULL;

	struct list_head *orig_head = NULL;

	struct perf_pmu *pmu = NULL;

	int ok = 0;

	char *config;
@@ -1674,7 +1675,6 @@ int parse_events_multi_pmu_add(struct parse_events_state *parse_state, 
	}

	list_add_tail(&term->list, head);





	/* Add it for all PMUs that support the alias */

	list = malloc(sizeof(struct list_head));

	if (!list)
@@ -1687,13 +1687,15 @@ int parse_events_multi_pmu_add(struct parse_events_state *parse_state, 


		list_for_each_entry(alias, &pmu->aliases, list) {

			if (!strcasecmp(alias->name, str)) {

				parse_events_copy_term_list(head, &orig_head);

				if (!parse_events_add_pmu(parse_state, list,

							  pmu->name, head,

							  pmu->name, orig_head,

							  true, true)) {

					pr_debug("%s -> %s/%s/\n", str,

						 pmu->name, alias->str);

					ok++;

				}

				parse_events_terms__delete(orig_head);

			}

		}

	}
@@ -2193,7 +2195,7 @@ int perf_pmu__test_parse_init(void) 
	for (i = 0; i < ARRAY_SIZE(symbols); i++, tmp++) {

		tmp->type = symbols[i].type;

		tmp->symbol = strdup(symbols[i].symbol);

		if (!list->symbol)

		if (!tmp->symbol)

			goto err_free;

	}