Commit aac2e96b authored by Paul Burton's avatar Paul Burton Committed by Bjorn Helgaas
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PCI: xilinx: Don't enable config completion interrupts 



The Xilinx AXI bridge for PCI Express device provides interrupts indicating
the completion of config space accesses. We have previously
enabled/unmasked them but do nothing with them besides acknowledge them.

Leave the interrupts masked in order to avoid servicing a large number of
pointless interrupts during boot.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Cc: Bharat Kumar Gogada <bharatku@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Ravikiran Gummaluri <rgummal@xilinx.com>
parent d0b5dda6

drivers/pci/host/pcie-xilinx.c

+3 −2
Original line number Diff line number Diff line
@@ -60,6 +60,7 @@ 
#define XILINX_PCIE_INTR_MST_SLVERR	BIT(27)

#define XILINX_PCIE_INTR_MST_ERRP	BIT(28)

#define XILINX_PCIE_IMR_ALL_MASK	0x1FF30FED

#define XILINX_PCIE_IMR_ENABLE_MASK	0x1FF30F0D

#define XILINX_PCIE_IDR_ALL_MASK	0xFFFFFFFF



/* Root Port Error FIFO Read Register definitions */
@@ -554,8 +555,8 @@ static void xilinx_pcie_init_port(struct xilinx_pcie_port *port) 
			 XILINX_PCIE_IMR_ALL_MASK,

		   XILINX_PCIE_REG_IDR);



	/* Enable all interrupts */

	pcie_write(port, XILINX_PCIE_IMR_ALL_MASK, XILINX_PCIE_REG_IMR);

	/* Enable all interrupts we handle */

	pcie_write(port, XILINX_PCIE_IMR_ENABLE_MASK, XILINX_PCIE_REG_IMR);



	/* Enable the Bridge enable bit */

	pcie_write(port, pcie_read(port, XILINX_PCIE_REG_RPSC) |