Commit aa5b537b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux 

Pull RISC-V updates from Palmer Dabbelt:

 - Support for Sv57-based virtual memory.

 - Various improvements for the MicroChip PolarFire SOC and the
   associated Icicle dev board, which should allow upstream kernels to
   boot without any additional modifications.

 - An improved memmove() implementation.

 - Support for the new Ssconfpmf and SBI PMU extensions, which allows
   for a much more useful perf implementation on RISC-V systems.

 - Support for restartable sequences.

* tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (36 commits)
  rseq/selftests: Add support for RISC-V
  RISC-V: Add support for restartable sequence
  MAINTAINERS: Add entry for RISC-V PMU drivers
  Documentation: riscv: Remove the old documentation
  RISC-V: Add sscofpmf extension support
  RISC-V: Add perf platform driver based on SBI PMU extension
  RISC-V: Add RISC-V SBI PMU extension definitions
  RISC-V: Add a simple platform driver for RISC-V legacy perf
  RISC-V: Add a perf core library for pmu drivers
  RISC-V: Add CSR encodings for all HPMCOUNTERS
  RISC-V: Remove the current perf implementation
  RISC-V: Improve /proc/cpuinfo output for ISA extensions
  RISC-V: Do no continue isa string parsing without correct XLEN
  RISC-V: Implement multi-letter ISA extension probing framework
  RISC-V: Extract multi-letter extension names from "riscv, isa"
  RISC-V: Minimal parser for "riscv, isa" strings
  RISC-V: Correctly print supported extensions
  riscv: Fixed misaligned memory access. Fixed pointer comparison.
  MAINTAINERS: update riscv/microchip entry
  riscv: dts: microchip: add new peripherals to icicle kit device tree
  ...
parents d710d370 bbde0152

Documentation/devicetree/bindings/clock/microchip,mpfs.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/microchip,mpfs.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Microchip PolarFire Clock Control Module Binding



maintainers:

  - Daire McNamara <daire.mcnamara@microchip.com>



description: |

  Microchip PolarFire clock control (CLKCFG) is an integrated clock controller,

  which gates and enables all peripheral clocks.



  This device tree binding describes 33 gate clocks.  Clocks are referenced by

  user nodes by the CLKCFG node phandle and the clock index in the group, from

  0 to 32.



properties:

  compatible:

    const: microchip,mpfs-clkcfg



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  '#clock-cells':

    const: 1

    description: |

      The clock consumer should specify the desired clock by having the clock

      ID in its "clocks" phandle cell. See include/dt-bindings/clock/microchip,mpfs-clock.h

      for the full list of PolarFire clock IDs.



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'



additionalProperties: false



examples:

  # Clock Config node:

  - |

    #include <dt-bindings/clock/microchip,mpfs-clock.h>

    soc {

            #address-cells = <2>;

            #size-cells = <2>;

            clkcfg: clock-controller@20002000 {

                compatible = "microchip,mpfs-clkcfg";

                reg = <0x0 0x20002000 0x0 0x1000>;

                clocks = <&ref>;

                #clock-cells = <1>;

        };

    };

Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Microchip MPFS GPIO Controller Device Tree Bindings



maintainers:

  - Conor Dooley <conor.dooley@microchip.com>



properties:

  compatible:

    items:

      - enum:

          - microchip,mpfs-gpio



  reg:

    maxItems: 1



  interrupts:

    description:

      Interrupt mapping, one per GPIO. Maximum 32 GPIOs.

    minItems: 1

    maxItems: 32



  interrupt-controller: true



  clocks:

    maxItems: 1



  "#gpio-cells":

    const: 2



  "#interrupt-cells":

    const: 1



  ngpios:

    description:

      The number of GPIOs available.

    minimum: 1

    maximum: 32

    default: 32



  gpio-controller: true



required:

  - compatible

  - reg

  - interrupts

  - "#interrupt-cells"

  - interrupt-controller

  - "#gpio-cells"

  - gpio-controller

  - clocks



additionalProperties: false



examples:

  - |

    gpio@20122000 {

        compatible = "microchip,mpfs-gpio";

        reg = <0x20122000 0x1000>;

        clocks = <&clkcfg 25>;

        interrupt-parent = <&plic>;

        gpio-controller;

        #gpio-cells = <2>;

        interrupt-controller;

        #interrupt-cells = <1>;

        interrupts = <53>, <53>, <53>, <53>,

                     <53>, <53>, <53>, <53>,

                     <53>, <53>, <53>, <53>,

                     <53>, <53>, <53>, <53>,

                     <53>, <53>, <53>, <53>,

                     <53>, <53>, <53>, <53>,

                     <53>, <53>, <53>, <53>,

                     <53>, <53>, <53>, <53>;

    };

...

Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml→Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/mailbox/microchip,polarfire-soc-mailbox.yaml#"

$id: "http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller
@@ -11,7 +11,7 @@ maintainers: 


properties:

  compatible:

    const: microchip,polarfire-soc-mailbox

    const: microchip,mpfs-mailbox



  reg:

    items:
@@ -38,7 +38,7 @@ examples: 
      #address-cells = <2>;

      #size-cells = <2>;

      mbox: mailbox@37020000 {

        compatible = "microchip,polarfire-soc-mailbox";

        compatible = "microchip,mpfs-mailbox";

        reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318c 0x0 0x40>;

        interrupt-parent = <&L1>;

        interrupts = <96>;

Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)



%YAML 1.2

---

$id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Microchip IP corePWM controller bindings



maintainers:

  - Conor Dooley <conor.dooley@microchip.com>



description: |

  corePWM is an 16 channel pulse width modulator FPGA IP



  https://www.microsemi.com/existing-parts/parts/152118



allOf:

  - $ref: pwm.yaml#



properties:

  compatible:

    items:

      - const: microchip,corepwm-rtl-v4



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  "#pwm-cells":

    const: 2



  microchip,sync-update-mask:

    description: |

      Depending on how the IP is instantiated, there are two modes of operation.

      In synchronous mode, all channels are updated at the beginning of the PWM period,

      and in asynchronous mode updates happen as the control registers are written.

      A 16 bit wide "SHADOW_REG_EN" parameter of the IP core controls whether synchronous

      mode is possible for each channel, and is set by the bitstream programmed to the

      FPGA. If the IP core is instantiated with SHADOW_REG_ENx=1, both registers that

      control the duty cycle for channel x have a second "shadow"/buffer reg synthesised.

      At runtime a bit wide register exposed to APB can be used to toggle on/off

      synchronised mode for all channels it has been synthesised for.

      Each bit of "microchip,sync-update-mask" corresponds to a PWM channel & represents

      whether synchronous mode is possible for the PWM channel.



    $ref: /schemas/types.yaml#/definitions/uint32

    default: 0



  microchip,dac-mode-mask:

    description: |

      Optional, per-channel Low Ripple DAC mode is possible on this IP core. It creates

      a minimum period pulse train whose High/Low average is that of the chosen duty

      cycle. This "DAC" will have far better bandwidth and ripple performance than the

      standard PWM algorithm can achieve. A 16 bit DAC_MODE module parameter of the IP

      core, set at instantiation and by the bitstream programmed to the FPGA, determines

      whether a given channel operates in regular PWM or DAC mode.

      Each bit corresponds to a PWM channel & represents whether DAC mode is enabled

      for that channel.



    $ref: /schemas/types.yaml#/definitions/uint32

    default: 0



required:

  - compatible

  - reg

  - clocks



additionalProperties: false



examples:

  - |

    pwm@41000000 {

      compatible = "microchip,corepwm-rtl-v4";

      microchip,sync-update-mask = /bits/ 32 <0>;

      clocks = <&clkcfg 30>;

      reg = <0x41000000 0xF0>;

      #pwm-cells = <2>;

    };

Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#



$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings



allOf:

  - $ref: rtc.yaml#



maintainers:

  - Daire McNamara <daire.mcnamara@microchip.com>

  - Lewis Hanly <lewis.hanly@microchip.com>



properties:

  compatible:

    enum:

      - microchip,mpfs-rtc



  reg:

    maxItems: 1



  interrupts:

    items:

      - description: |

          RTC_WAKEUP interrupt

      - description: |

          RTC_MATCH, asserted when the content of the Alarm register is equal

          to that of the RTC's count register.



  clocks:

    maxItems: 1



  clock-names:

    items:

      - const: rtc



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names



additionalProperties: false



examples:

  - |

    rtc@20124000 {

        compatible = "microchip,mpfs-rtc";

        reg = <0x20124000 0x1000>;

        clocks = <&clkcfg 21>;

        clock-names = "rtc";

        interrupts = <80>, <81>;

    };

...