Commit aa50479b authored by Mark Brown's avatar Mark Brown Committed by Will Deacon
Browse files

arm64/sysreg: Add _EL1 into ID_AA64ISAR1_EL1 definition names 



Normally we include the full register name in the defines for fields within
registers but this has not been followed for ID registers. In preparation
for automatic generation of defines add the _EL1s into the defines for
ID_AA64ISAR1_EL1 to follow the convention. No functional changes.

Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220704170302.2609529-16-broonie@kernel.org


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent b7e4a2d7

arch/arm64/include/asm/asm_pointer_auth.h

+1 −1
Original line number Diff line number Diff line
@@ -59,7 +59,7 @@ alternative_else_nop_endif 


	.macro __ptrauth_keys_init_cpu tsk, tmp1, tmp2, tmp3

	mrs	\tmp1, id_aa64isar1_el1

	ubfx	\tmp1, \tmp1, #ID_AA64ISAR1_APA_SHIFT, #8

	ubfx	\tmp1, \tmp1, #ID_AA64ISAR1_EL1_APA_SHIFT, #8

	mrs_s	\tmp2, SYS_ID_AA64ISAR2_EL1

	ubfx	\tmp2, \tmp2, #ID_AA64ISAR2_APA3_SHIFT, #4

	orr	\tmp1, \tmp1, \tmp2

arch/arm64/include/asm/sysreg.h

+31 −31
Original line number Diff line number Diff line
@@ -705,37 +705,37 @@ 
#define MAIR_ATTRIDX(attr, idx)		((attr) << ((idx) * 8))



/* id_aa64isar1 */

#define ID_AA64ISAR1_I8MM_SHIFT		52

#define ID_AA64ISAR1_DGH_SHIFT		48

#define ID_AA64ISAR1_BF16_SHIFT		44

#define ID_AA64ISAR1_SPECRES_SHIFT	40

#define ID_AA64ISAR1_SB_SHIFT		36

#define ID_AA64ISAR1_FRINTTS_SHIFT	32

#define ID_AA64ISAR1_GPI_SHIFT		28

#define ID_AA64ISAR1_GPA_SHIFT		24

#define ID_AA64ISAR1_LRCPC_SHIFT	20

#define ID_AA64ISAR1_FCMA_SHIFT		16

#define ID_AA64ISAR1_JSCVT_SHIFT	12

#define ID_AA64ISAR1_API_SHIFT		8

#define ID_AA64ISAR1_APA_SHIFT		4

#define ID_AA64ISAR1_DPB_SHIFT		0



#define ID_AA64ISAR1_APA_NI			0x0

#define ID_AA64ISAR1_APA_PAuth			0x1

#define ID_AA64ISAR1_APA_ARCH_EPAC		0x2

#define ID_AA64ISAR1_APA_Pauth2			0x3

#define ID_AA64ISAR1_APA_FPAC			0x4

#define ID_AA64ISAR1_APA_FPACCOMBINE		0x5

#define ID_AA64ISAR1_API_NI			0x0

#define ID_AA64ISAR1_API_PAuth			0x1

#define ID_AA64ISAR1_API_EPAC			0x2

#define ID_AA64ISAR1_API_PAuth2			0x3

#define ID_AA64ISAR1_API_FPAC			0x4

#define ID_AA64ISAR1_API_FPACCOMBINE		0x5

#define ID_AA64ISAR1_GPA_NI			0x0

#define ID_AA64ISAR1_GPA_IMP			0x1

#define ID_AA64ISAR1_GPI_NI			0x0

#define ID_AA64ISAR1_GPI_IMP			0x1

#define ID_AA64ISAR1_EL1_I8MM_SHIFT		52

#define ID_AA64ISAR1_EL1_DGH_SHIFT		48

#define ID_AA64ISAR1_EL1_BF16_SHIFT		44

#define ID_AA64ISAR1_EL1_SPECRES_SHIFT		40

#define ID_AA64ISAR1_EL1_SB_SHIFT		36

#define ID_AA64ISAR1_EL1_FRINTTS_SHIFT		32

#define ID_AA64ISAR1_EL1_GPI_SHIFT		28

#define ID_AA64ISAR1_EL1_GPA_SHIFT		24

#define ID_AA64ISAR1_EL1_LRCPC_SHIFT		20

#define ID_AA64ISAR1_EL1_FCMA_SHIFT		16

#define ID_AA64ISAR1_EL1_JSCVT_SHIFT		12

#define ID_AA64ISAR1_EL1_API_SHIFT		8

#define ID_AA64ISAR1_EL1_APA_SHIFT		5

#define ID_AA64ISAR1_EL1_DPB_SHIFT		0



#define ID_AA64ISAR1_EL1_APA_NI			0x0

#define ID_AA64ISAR1_EL1_APA_PAuth		0x1

#define ID_AA64ISAR1_EL1_APA_ARCH_EPAC		0x2

#define ID_AA64ISAR1_EL1_APA_Pauth2		0x3

#define ID_AA64ISAR1_EL1_APA_FPAC		0x4

#define ID_AA64ISAR1_EL1_APA_FPACCOMBINE	0x5

#define ID_AA64ISAR1_EL1_API_NI			0x0

#define ID_AA64ISAR1_EL1_API_PAuth		0x1

#define ID_AA64ISAR1_EL1_API_EPAC		0x2

#define ID_AA64ISAR1_EL1_API_PAuth2		0x3

#define ID_AA64ISAR1_EL1_API_FPAC		0x4

#define ID_AA64ISAR1_EL1_API_FPACCOMBINE	0x5

#define ID_AA64ISAR1_EL1_GPA_NI			0x0

#define ID_AA64ISAR1_EL1_GPA_IMP		0x1

#define ID_AA64ISAR1_EL1_GPI_NI			0x0

#define ID_AA64ISAR1_EL1_GPI_IMP		0x1



/* id_aa64isar2 */

#define ID_AA64ISAR2_BC_SHIFT		28

arch/arm64/kernel/cpufeature.c

+45 −45
Original line number Diff line number Diff line
@@ -209,24 +209,24 @@ static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 
};



static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),

		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),

		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),

		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),

		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),

		       FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0),

		       FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),

		       FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),

		       FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0),

	ARM64_FTR_END,

};
@@ -2132,7 +2132,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.type = ARM64_CPUCAP_SYSTEM_FEATURE,

		.matches = has_cpuid_feature,

		.sys_reg = SYS_ID_AA64ISAR1_EL1,

		.field_pos = ID_AA64ISAR1_DPB_SHIFT,

		.field_pos = ID_AA64ISAR1_EL1_DPB_SHIFT,

		.field_width = 4,

		.min_field_value = 1,

	},
@@ -2143,7 +2143,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.matches = has_cpuid_feature,

		.sys_reg = SYS_ID_AA64ISAR1_EL1,

		.sign = FTR_UNSIGNED,

		.field_pos = ID_AA64ISAR1_DPB_SHIFT,

		.field_pos = ID_AA64ISAR1_EL1_DPB_SHIFT,

		.field_width = 4,

		.min_field_value = 2,

	},
@@ -2303,7 +2303,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.type = ARM64_CPUCAP_SYSTEM_FEATURE,

		.matches = has_cpuid_feature,

		.sys_reg = SYS_ID_AA64ISAR1_EL1,

		.field_pos = ID_AA64ISAR1_SB_SHIFT,

		.field_pos = ID_AA64ISAR1_EL1_SB_SHIFT,

		.field_width = 4,

		.sign = FTR_UNSIGNED,

		.min_field_value = 1,
@@ -2315,9 +2315,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,

		.sys_reg = SYS_ID_AA64ISAR1_EL1,

		.sign = FTR_UNSIGNED,

		.field_pos = ID_AA64ISAR1_APA_SHIFT,

		.field_pos = ID_AA64ISAR1_EL1_APA_SHIFT,

		.field_width = 4,

		.min_field_value = ID_AA64ISAR1_APA_PAuth,

		.min_field_value = ID_AA64ISAR1_EL1_APA_PAuth,

		.matches = has_address_auth_cpucap,

	},

	{
@@ -2337,9 +2337,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,

		.sys_reg = SYS_ID_AA64ISAR1_EL1,

		.sign = FTR_UNSIGNED,

		.field_pos = ID_AA64ISAR1_API_SHIFT,

		.field_pos = ID_AA64ISAR1_EL1_API_SHIFT,

		.field_width = 4,

		.min_field_value = ID_AA64ISAR1_API_PAuth,

		.min_field_value = ID_AA64ISAR1_EL1_API_PAuth,

		.matches = has_address_auth_cpucap,

	},

	{
@@ -2353,9 +2353,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.type = ARM64_CPUCAP_SYSTEM_FEATURE,

		.sys_reg = SYS_ID_AA64ISAR1_EL1,

		.sign = FTR_UNSIGNED,

		.field_pos = ID_AA64ISAR1_GPA_SHIFT,

		.field_pos = ID_AA64ISAR1_EL1_GPA_SHIFT,

		.field_width = 4,

		.min_field_value = ID_AA64ISAR1_GPA_IMP,

		.min_field_value = ID_AA64ISAR1_EL1_GPA_IMP,

		.matches = has_cpuid_feature,

	},

	{
@@ -2375,9 +2375,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.type = ARM64_CPUCAP_SYSTEM_FEATURE,

		.sys_reg = SYS_ID_AA64ISAR1_EL1,

		.sign = FTR_UNSIGNED,

		.field_pos = ID_AA64ISAR1_GPI_SHIFT,

		.field_pos = ID_AA64ISAR1_EL1_GPI_SHIFT,

		.field_width = 4,

		.min_field_value = ID_AA64ISAR1_GPI_IMP,

		.min_field_value = ID_AA64ISAR1_EL1_GPI_IMP,

		.matches = has_cpuid_feature,

	},

	{
@@ -2478,7 +2478,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.type = ARM64_CPUCAP_SYSTEM_FEATURE,

		.sys_reg = SYS_ID_AA64ISAR1_EL1,

		.sign = FTR_UNSIGNED,

		.field_pos = ID_AA64ISAR1_LRCPC_SHIFT,

		.field_pos = ID_AA64ISAR1_EL1_LRCPC_SHIFT,

		.field_width = 4,

		.matches = has_cpuid_feature,

		.min_field_value = 1,
@@ -2560,33 +2560,33 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
#ifdef CONFIG_ARM64_PTR_AUTH

static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {

	{

		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,

		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_APA_SHIFT,

				  4, FTR_UNSIGNED,

				  ID_AA64ISAR1_APA_PAuth)

				  ID_AA64ISAR1_EL1_APA_PAuth)

	},

	{

		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_APA3_SHIFT,

				  4, FTR_UNSIGNED, ID_AA64ISAR2_APA3_PAuth)

	},

	{

		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,

				  4, FTR_UNSIGNED, ID_AA64ISAR1_API_PAuth)

		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_API_SHIFT,

				  4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_API_PAuth)

	},

	{},

};



static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {

	{

		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,

				  4, FTR_UNSIGNED, ID_AA64ISAR1_GPA_IMP)

		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPA_SHIFT,

				  4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPA_IMP)

	},

	{

		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_GPA3_SHIFT,

				  4, FTR_UNSIGNED, ID_AA64ISAR2_GPA3_IMP)

	},

	{

		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,

				  4, FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP)

		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPI_SHIFT,

				  4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPI_IMP)

	},

	{},

};
@@ -2614,17 +2614,17 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 
	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),

	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),

	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_SB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM),

	HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),

#ifdef CONFIG_ARM64_SVE

	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),

arch/arm64/kernel/idreg-override.c

+4 −4
Original line number Diff line number Diff line
@@ -63,10 +63,10 @@ static const struct ftr_set_desc isar1 __initconst = { 
	.name		= "id_aa64isar1",

	.override	= &id_aa64isar1_override,

	.fields		= {

		{ "gpi", ID_AA64ISAR1_GPI_SHIFT },

		{ "gpa", ID_AA64ISAR1_GPA_SHIFT },

		{ "api", ID_AA64ISAR1_API_SHIFT },

		{ "apa", ID_AA64ISAR1_APA_SHIFT },

		{ "gpi", ID_AA64ISAR1_EL1_GPI_SHIFT },

		{ "gpa", ID_AA64ISAR1_EL1_GPA_SHIFT },

		{ "api", ID_AA64ISAR1_EL1_API_SHIFT },

		{ "apa", ID_AA64ISAR1_EL1_APA_SHIFT },

		{}

	},

};

arch/arm64/kvm/hyp/include/nvhe/fixed_config.h

+14 −14
Original line number Diff line number Diff line
@@ -176,20 +176,20 @@ 
	)



#define PVM_ID_AA64ISAR1_ALLOW (\

	ARM64_FEATURE_MASK(ID_AA64ISAR1_DPB) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_APA) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_API) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_JSCVT) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_FCMA) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_LRCPC) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_GPA) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_GPI) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_FRINTTS) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_SB) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_SPECRES) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_BF16) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_DGH) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_I8MM) \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_DPB) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_JSCVT) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_FCMA) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_LRCPC) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_FRINTTS) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_SB) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_SPECRES) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_BF16) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_DGH) | \

	ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_I8MM) \

	)



#define PVM_ID_AA64ISAR2_ALLOW (\