Commit aa193f7e authored by Hamza Mahfooz's avatar Hamza Mahfooz Committed by Alex Deucher
Browse files

drm/edid: add a quirk for two LG monitors to get them to work on 10bpc 



The LG 27GP950 and LG 27GN950 have visible display corruption when
trying to use 10bpc modes. So, to fix this, cap their maximum DSC
target bitrate to 15bpp.

Suggested-by: default avatarRoman Li <roman.li@amd.com>
Reviewed-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c9bdc6c3

drivers/gpu/drm/drm_edid.c

+12 −0
Original line number Diff line number Diff line
@@ -87,6 +87,8 @@ static int oui(u8 first, u8 second, u8 third) 
#define EDID_QUIRK_FORCE_10BPC			(1 << 11)

/* Non desktop display (i.e. HMD) */

#define EDID_QUIRK_NON_DESKTOP			(1 << 12)

/* Cap the DSC target bitrate to 15bpp */

#define EDID_QUIRK_CAP_DSC_15BPP		(1 << 13)



#define MICROSOFT_IEEE_OUI	0xca125c
@@ -147,6 +149,12 @@ static const struct edid_quirk { 
	EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |

				       EDID_QUIRK_DETAILED_IN_CM),



	/* LG 27GP950 */

	EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP),



	/* LG 27GN950 */

	EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP),



	/* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */

	EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
@@ -6166,6 +6174,7 @@ static void drm_reset_display_info(struct drm_connector *connector) 


	info->mso_stream_count = 0;

	info->mso_pixel_overlap = 0;

	info->max_dsc_bpp = 0;

}



static u32 update_display_info(struct drm_connector *connector,
@@ -6252,6 +6261,9 @@ static u32 update_display_info(struct drm_connector *connector, 
		info->non_desktop = true;

	}



	if (quirks & EDID_QUIRK_CAP_DSC_15BPP)

		info->max_dsc_bpp = 15;



	return quirks;

}

include/drm/drm_connector.h

+6 −0
Original line number Diff line number Diff line
@@ -656,6 +656,12 @@ struct drm_display_info { 
	 * @mso_pixel_overlap: eDP MSO segment pixel overlap, 0-8 pixels.

	 */

	u8 mso_pixel_overlap;



	/**

	 * @max_dsc_bpp: Maximum DSC target bitrate, if it is set to 0 the

	 * monitor's default value is used instead.

	 */

	u32 max_dsc_bpp;

};



int drm_display_info_set_bus_formats(struct drm_display_info *info,