Commit a9c3abf4 authored by Gaosheng Cui's avatar Gaosheng Cui Committed by Jakub Kicinski
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mlxsw: reg: Remove deprecated code about SFTR-V2 Register 



Remove all the code about SFTR-V2 Register which have been
deprecated since commit 77b7f83d ("mlxsw: Enable unified
bridge model").

Signed-off-by: default avatarGaosheng Cui <cuigaosheng1@huawei.com>
Reviewed-by: default avatarIdo Schimmel <idosch@nvidia.com>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 56378f3c

drivers/net/ethernet/mellanox/mlxsw/reg.h

+0 −71
Original line number Diff line number Diff line
@@ -2218,76 +2218,6 @@ static inline void mlxsw_reg_smpe_pack(char *payload, u16 local_port, 
	mlxsw_reg_smpe_evid_set(payload, evid);

}



/* SFTR-V2 - Switch Flooding Table Version 2 Register

 * --------------------------------------------------

 * The switch flooding table is used for flooding packet replication. The table

 * defines a bit mask of ports for packet replication.

 */

#define MLXSW_REG_SFTR2_ID 0x202F

#define MLXSW_REG_SFTR2_LEN 0x120



MLXSW_REG_DEFINE(sftr2, MLXSW_REG_SFTR2_ID, MLXSW_REG_SFTR2_LEN);



/* reg_sftr2_swid

 * Switch partition ID with which to associate the port.

 * Access: Index

 */

MLXSW_ITEM32(reg, sftr2, swid, 0x00, 24, 8);



/* reg_sftr2_flood_table

 * Flooding table index to associate with the specific type on the specific

 * switch partition.

 * Access: Index

 */

MLXSW_ITEM32(reg, sftr2, flood_table, 0x00, 16, 6);



/* reg_sftr2_index

 * Index. Used as an index into the Flooding Table in case the table is

 * configured to use VID / FID or FID Offset.

 * Access: Index

 */

MLXSW_ITEM32(reg, sftr2, index, 0x00, 0, 16);



/* reg_sftr2_table_type

 * See mlxsw_flood_table_type

 * Access: RW

 */

MLXSW_ITEM32(reg, sftr2, table_type, 0x04, 16, 3);



/* reg_sftr2_range

 * Range of entries to update

 * Access: Index

 */

MLXSW_ITEM32(reg, sftr2, range, 0x04, 0, 16);



/* reg_sftr2_port

 * Local port membership (1 bit per port).

 * Access: RW

 */

MLXSW_ITEM_BIT_ARRAY(reg, sftr2, port, 0x20, 0x80, 1);



/* reg_sftr2_port_mask

 * Local port mask (1 bit per port).

 * Access: WO

 */

MLXSW_ITEM_BIT_ARRAY(reg, sftr2, port_mask, 0xA0, 0x80, 1);



static inline void mlxsw_reg_sftr2_pack(char *payload,

					unsigned int flood_table,

					unsigned int index,

					enum mlxsw_flood_table_type table_type,

					unsigned int range, u16 port, bool set)

{

	MLXSW_REG_ZERO(sftr2, payload);

	mlxsw_reg_sftr2_swid_set(payload, 0);

	mlxsw_reg_sftr2_flood_table_set(payload, flood_table);

	mlxsw_reg_sftr2_index_set(payload, index);

	mlxsw_reg_sftr2_table_type_set(payload, table_type);

	mlxsw_reg_sftr2_range_set(payload, range);

	mlxsw_reg_sftr2_port_set(payload, port, set);

	mlxsw_reg_sftr2_port_mask_set(payload, port, 1);

}



/* SMID-V2 - Switch Multicast ID Version 2 Register

 * ------------------------------------------------

 * The MID record maps from a MID (Multicast ID), which is a unique identifier
@@ -12833,7 +12763,6 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 
	MLXSW_REG(spvc),

	MLXSW_REG(spevet),

	MLXSW_REG(smpe),

	MLXSW_REG(sftr2),

	MLXSW_REG(smid2),

	MLXSW_REG(cwtp),

	MLXSW_REG(cwtpm),