Commit a9843ce6 authored by Sandipan Das's avatar Sandipan Das Committed by Wenkuan Wang
Browse files

perf/x86/amd/core: Update and fix stalled-cycles-* events for Zen 2 and later 

mainline inclusion
from mainline-v6.9-rc2
commit c7b2edd8377be983442c1344cb940cd2ac21b601
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I9HG74


CVE: NA

--------------------------------

AMD processors based on Zen 2 and later microarchitectures do not
support PMCx087 (instruction pipe stalls) which is used as the backing
event for "stalled-cycles-frontend" and "stalled-cycles-backend".

Use PMCx0A9 (cycles where micro-op queue is empty) instead to count
frontend stalls and remove the entry for backend stalls since there
is no direct replacement.

Signed-off-by: default avatarSandipan Das <sandipan.das@amd.com>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
Reviewed-by: default avatarIan Rogers <irogers@google.com>
Fixes: 3fe3331b ("perf/x86/amd: Add event map for AMD Family 17h")
Link: https://lore.kernel.org/r/03d7fc8fa2a28f9be732116009025bdec1b3ec97.1711352180.git.sandipan.das@amd.com


Signed-off-by: default avatarWenkuan Wang <Wenkuan.Wang@amd.com>
parent efe92608

arch/x86/events/amd/core.c

+17 −3
Original line number Diff line number Diff line
@@ -250,7 +250,7 @@ static const u64 amd_perfmon_event_map[PERF_COUNT_HW_MAX] = 
/*

 * AMD Performance Monitor Family 17h and later:

 */

static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] =

static const u64 amd_zen1_perfmon_event_map[PERF_COUNT_HW_MAX] =

{

	[PERF_COUNT_HW_CPU_CYCLES]		= 0x0076,

	[PERF_COUNT_HW_INSTRUCTIONS]		= 0x00c0,
@@ -262,10 +262,24 @@ static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] = 
	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND]	= 0x0187,

};



static const u64 amd_zen2_perfmon_event_map[PERF_COUNT_HW_MAX] =

{

	[PERF_COUNT_HW_CPU_CYCLES]		= 0x0076,

	[PERF_COUNT_HW_INSTRUCTIONS]		= 0x00c0,

	[PERF_COUNT_HW_CACHE_REFERENCES]	= 0xff60,

	[PERF_COUNT_HW_CACHE_MISSES]		= 0x0964,

	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= 0x00c2,

	[PERF_COUNT_HW_BRANCH_MISSES]		= 0x00c3,

	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]	= 0x00a9,

};



static u64 amd_pmu_event_map(int hw_event)

{

	if (boot_cpu_data.x86 >= 0x17)

		return amd_f17h_perfmon_event_map[hw_event];

	if (cpu_feature_enabled(X86_FEATURE_ZEN2) || boot_cpu_data.x86 >= 0x19)

		return amd_zen2_perfmon_event_map[hw_event];



	if (cpu_feature_enabled(X86_FEATURE_ZEN1))

		return amd_zen1_perfmon_event_map[hw_event];



	return amd_perfmon_event_map[hw_event];

}