Commit a97dd9e2 authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc/fsl_booke: Enable reloading of TLBCAM without switching to AS1 



Avoid switching to AS1 when reloading TLBCAM after init for
STRICT_KERNEL_RWX.

When we setup AS1 we expect the entire accessible memory to be mapped
through one entry, this is not the case anymore at the end of init.

We are not changing the size of TLBCAMs, only flags, so no need to
switch to AS1.

So change loadcam_multi() to not switch to AS1 when the given
temporary tlb entry in 0.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/a9d517fbfbc940f56103c46b323f6eb8f4485571.1634292136.git.christophe.leroy@csgroup.eu
parent 01116e6e

arch/powerpc/mm/nohash/tlb_low.S

+6 −2
Original line number Diff line number Diff line
@@ -369,7 +369,7 @@ _GLOBAL(_tlbivax_bcast) 
 * extern void loadcam_entry(unsigned int index)

 *

 * Load TLBCAM[index] entry in to the L2 CAM MMU

 * Must preserve r7, r8, r9, r10 and r11

 * Must preserve r7, r8, r9, r10, r11, r12

 */

_GLOBAL(loadcam_entry)

	mflr	r5
@@ -401,7 +401,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS) 
 *

 * r3 = first entry to write

 * r4 = number of entries to write

 * r5 = temporary tlb entry

 * r5 = temporary tlb entry (0 means no switch to AS1)

 */

_GLOBAL(loadcam_multi)

	mflr	r8
@@ -409,6 +409,8 @@ _GLOBAL(loadcam_multi) 
	mfmsr	r11

	andi.	r11,r11,MSR_IS

	bne	10f

	mr.	r12, r5

	beq	10f



	/*

	 * Set up temporary TLB entry that is the same as what we're
@@ -446,6 +448,8 @@ _GLOBAL(loadcam_multi) 
	/* Don't return to AS=0 if we were in AS=1 at function start */

	andi.	r11,r11,MSR_IS

	bne	3f

	cmpwi	r12, 0

	beq	3f



	/* Return to AS=0 and clear the temporary entry */

	mfmsr	r6