Commit a96d3a5b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86_urgent_for_v5.17_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 fixes from Borislav Petkov:

 - Add another Intel CPU model to the list of CPUs supporting the
   processor inventory unique number

 - Allow writing to MCE thresholding sysfs files again - a previous
   change had accidentally disabled it and no one noticed. Goes to show
   how much is this stuff used

* tag 'x86_urgent_for_v5.17_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN
  x86/MCE/AMD: Allow thresholding interface updates after init
parents 8dd71685 e464121f

arch/x86/kernel/cpu/mce/amd.c

+1 −1
Original line number Diff line number Diff line
@@ -423,7 +423,7 @@ static void threshold_restart_bank(void *_tr) 
	u32 hi, lo;



	/* sysfs write might race against an offline operation */

	if (this_cpu_read(threshold_banks))

	if (!this_cpu_read(threshold_banks) && !tr->set_lvt_off)

		return;



	rdmsr(tr->b->address, lo, hi);

arch/x86/kernel/cpu/mce/intel.c

+1 −0
Original line number Diff line number Diff line
@@ -486,6 +486,7 @@ static void intel_ppin_init(struct cpuinfo_x86 *c) 
	case INTEL_FAM6_BROADWELL_X:

	case INTEL_FAM6_SKYLAKE_X:

	case INTEL_FAM6_ICELAKE_X:

	case INTEL_FAM6_ICELAKE_D:

	case INTEL_FAM6_SAPPHIRERAPIDS_X:

	case INTEL_FAM6_XEON_PHI_KNL:

	case INTEL_FAM6_XEON_PHI_KNM: