Commit a95eb1d0 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'loongarch-fixes-5.19-5' of... 

Merge tag 'loongarch-fixes-5.19-5' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson

Pull LoongArch fixes from Huacai Chen:

 - Fix cache size calculation, stack protection attributes, ptrace's
   fpr_set and "ROM Size" in boardinfo

 - Some cleanups and improvements of assembly

 - Some cleanups of unused code and useless code

* tag 'loongarch-fixes-5.19-5' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson:
  LoongArch: Fix wrong "ROM Size" of boardinfo
  LoongArch: Fix missing fcsr in ptrace's fpr_set
  LoongArch: Fix shared cache size calculation
  LoongArch: Disable executable stack by default
  LoongArch: Remove unused variables
  LoongArch: Remove clock setting during cpu hotplug stage
  LoongArch: Remove useless header compiler.h
  LoongArch: Remove several syntactic sugar macros for branches
  LoongArch: Re-tab the assembly files
  LoongArch: Simplify "BGT foo, zero" with BGTZ
  LoongArch: Simplify "BLT foo, zero" with BLTZ
  LoongArch: Simplify "BEQ/BNE foo, zero" with BEQZ/BNEZ
  LoongArch: Use the "move" pseudo-instruction where applicable
  LoongArch: Use the "jr" pseudo-instruction where applicable
  LoongArch: Use ABI names of registers where appropriate
parents 9d928d9b 45b53c90

arch/loongarch/Kconfig

+0 −1
Original line number Diff line number Diff line
@@ -69,7 +69,6 @@ config LOONGARCH 
	select GENERIC_TIME_VSYSCALL

	select GPIOLIB

	select HAVE_ARCH_AUDITSYSCALL

	select HAVE_ARCH_COMPILER_H

	select HAVE_ARCH_MMAP_RND_BITS if MMU

	select HAVE_ARCH_SECCOMP_FILTER

	select HAVE_ARCH_TRACEHOOK

arch/loongarch/include/asm/asmmacro.h

+0 −12
Original line number Diff line number Diff line
@@ -274,16 +274,4 @@ 
	nor	\dst, \src, zero

.endm



.macro bgt r0 r1 label

	blt	\r1, \r0, \label

.endm



.macro bltz r0 label

	blt	\r0, zero, \label

.endm



.macro bgez r0 label

	bge	\r0, zero, \label

.endm



#endif /* _ASM_ASMMACRO_H */

arch/loongarch/include/asm/atomic.h

+16 −21
Original line number Diff line number Diff line
@@ -10,7 +10,6 @@ 
#include <linux/types.h>

#include <asm/barrier.h>

#include <asm/cmpxchg.h>

#include <asm/compiler.h>



#if __SIZEOF_LONG__ == 4

#define __LL		"ll.w	"
@@ -157,27 +156,25 @@ static inline int arch_atomic_sub_if_positive(int i, atomic_t *v) 
		__asm__ __volatile__(

		"1:	ll.w	%1, %2		# atomic_sub_if_positive\n"

		"	addi.w	%0, %1, %3				\n"

		"	or	%1, %0, $zero				\n"

		"	blt	%0, $zero, 2f				\n"

		"	move	%1, %0					\n"

		"	bltz	%0, 2f					\n"

		"	sc.w	%1, %2					\n"

		"	beq	$zero, %1, 1b				\n"

		"	beqz	%1, 1b					\n"

		"2:							\n"

		__WEAK_LLSC_MB

		: "=&r" (result), "=&r" (temp),

		  "+" GCC_OFF_SMALL_ASM() (v->counter)

		: "=&r" (result), "=&r" (temp), "+ZC" (v->counter)

		: "I" (-i));

	} else {

		__asm__ __volatile__(

		"1:	ll.w	%1, %2		# atomic_sub_if_positive\n"

		"	sub.w	%0, %1, %3				\n"

		"	or	%1, %0, $zero				\n"

		"	blt	%0, $zero, 2f				\n"

		"	move	%1, %0					\n"

		"	bltz	%0, 2f					\n"

		"	sc.w	%1, %2					\n"

		"	beq	$zero, %1, 1b				\n"

		"	beqz	%1, 1b					\n"

		"2:							\n"

		__WEAK_LLSC_MB

		: "=&r" (result), "=&r" (temp),

		  "+" GCC_OFF_SMALL_ASM() (v->counter)

		: "=&r" (result), "=&r" (temp), "+ZC" (v->counter)

		: "r" (i));

	}
@@ -320,27 +317,25 @@ static inline long arch_atomic64_sub_if_positive(long i, atomic64_t *v) 
		__asm__ __volatile__(

		"1:	ll.d	%1, %2	# atomic64_sub_if_positive	\n"

		"	addi.d	%0, %1, %3				\n"

		"	or	%1, %0, $zero				\n"

		"	blt	%0, $zero, 2f				\n"

		"	move	%1, %0					\n"

		"	bltz	%0, 2f					\n"

		"	sc.d	%1, %2					\n"

		"	beq	%1, $zero, 1b				\n"

		"	beqz	%1, 1b					\n"

		"2:							\n"

		__WEAK_LLSC_MB

		: "=&r" (result), "=&r" (temp),

		  "+" GCC_OFF_SMALL_ASM() (v->counter)

		: "=&r" (result), "=&r" (temp), "+ZC" (v->counter)

		: "I" (-i));

	} else {

		__asm__ __volatile__(

		"1:	ll.d	%1, %2	# atomic64_sub_if_positive	\n"

		"	sub.d	%0, %1, %3				\n"

		"	or	%1, %0, $zero				\n"

		"	blt	%0, $zero, 2f				\n"

		"	move	%1, %0					\n"

		"	bltz	%0, 2f					\n"

		"	sc.d	%1, %2					\n"

		"	beq	%1, $zero, 1b				\n"

		"	beqz	%1, 1b					\n"

		"2:							\n"

		__WEAK_LLSC_MB

		: "=&r" (result), "=&r" (temp),

		  "+" GCC_OFF_SMALL_ASM() (v->counter)

		: "=&r" (result), "=&r" (temp), "+ZC" (v->counter)

		: "r" (i));

	}

arch/loongarch/include/asm/barrier.h

+2 −2
Original line number Diff line number Diff line
@@ -48,9 +48,9 @@ static inline unsigned long array_index_mask_nospec(unsigned long index, 
	__asm__ __volatile__(

		"sltu	%0, %1, %2\n\t"

#if (__SIZEOF_LONG__ == 4)

		"sub.w	%0, $r0, %0\n\t"

		"sub.w	%0, $zero, %0\n\t"

#elif (__SIZEOF_LONG__ == 8)

		"sub.d	%0, $r0, %0\n\t"

		"sub.d	%0, $zero, %0\n\t"

#endif

		: "=r" (mask)

		: "r" (index), "r" (size)

arch/loongarch/include/asm/cmpxchg.h

+2 −2
Original line number Diff line number Diff line
@@ -55,9 +55,9 @@ static inline unsigned long __xchg(volatile void *ptr, unsigned long x, 
	__asm__ __volatile__(						\

	"1:	" ld "	%0, %2		# __cmpxchg_asm \n"		\

	"	bne	%0, %z3, 2f			\n"		\

	"	or	$t0, %z4, $zero			\n"		\

	"	move	$t0, %z4			\n"		\

	"	" st "	$t0, %1				\n"		\

	"	beq	$zero, $t0, 1b			\n"		\

	"	beqz	$t0, 1b				\n"		\

	"2:						\n"		\

	__WEAK_LLSC_MB							\

	: "=&r" (__ret), "=ZB"(*m)					\