Commit a95ab935 authored by Ratheesh Kannoth's avatar Ratheesh Kannoth Committed by David S. Miller
Browse files

octeontx2-af: Use hashed field in MCAM key 



CN10KB variant of CN10K series of silicons supports
a new feature where in a large protocol field
(eg 128bit IPv6 DIP) can be condensed into a small
hashed 32bit data. This saves a lot of space in MCAM key
and allows user to add more protocol fields into the filter.
A max of two such protocol data can be hashed.
This patch adds support for hashing IPv6 SIP and/or DIP.

Signed-off-by: default avatarSuman Ghosh <sumang@marvell.com>
Signed-off-by: default avatarRatheesh Kannoth <rkannoth@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent e7ce9fc9

drivers/net/ethernet/marvell/octeontx2/af/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -11,4 +11,4 @@ rvu_mbox-y := mbox.o rvu_trace.o 
rvu_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \

		  rvu_reg.o rvu_npc.o rvu_debugfs.o ptp.o rvu_npc_fs.o \

		  rvu_cpt.o rvu_devlink.o rpm.o rvu_cn10k.o rvu_switch.o \

		  rvu_sdp.o
 
		  rvu_sdp.o rvu_npc_hash.o

drivers/net/ethernet/marvell/octeontx2/af/mbox.h

+14 −0
Original line number Diff line number Diff line
@@ -241,6 +241,9 @@ M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \ 
M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats,                     \

				   npc_mcam_get_stats_req,              \

				   npc_mcam_get_stats_rsp)              \

M(NPC_GET_SECRET_KEY, 0x6013, npc_get_secret_key,                     \

				   npc_get_secret_key_req,              \

				   npc_get_secret_key_rsp)              \

/* NIX mbox IDs (range 0x8000 - 0xFFFF) */				\

M(NIX_LF_ALLOC,		0x8000, nix_lf_alloc,				\

				 nix_lf_alloc_req, nix_lf_alloc_rsp)	\
@@ -428,6 +431,7 @@ struct get_hw_cap_rsp { 
	struct mbox_msghdr hdr;

	u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */

	u8 nix_shaping;		     /* Is shaping and coloring supported */

	u8 npc_hash_extract;	/* Is hash extract supported */

};



/* CGX mbox message formats */
@@ -1440,6 +1444,16 @@ struct npc_mcam_get_stats_rsp { 
	u8 stat_ena; /* enabled */

};



struct npc_get_secret_key_req {

	struct mbox_msghdr hdr;

	u8 intf;

};



struct npc_get_secret_key_rsp {

	struct mbox_msghdr hdr;

	u64 secret_key[3];

};



enum ptp_op {

	PTP_OP_ADJFINE = 0,

	PTP_OP_GET_CLOCK = 1,

drivers/net/ethernet/marvell/octeontx2/af/npc.h

+8 −0
Original line number Diff line number Diff line
@@ -10,6 +10,14 @@ 


#define NPC_KEX_CHAN_MASK	0xFFFULL



#define SET_KEX_LD(intf, lid, ltype, ld, cfg)	\

	rvu_write64(rvu, blkaddr,	\

		    NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, ltype, ld), cfg)



#define SET_KEX_LDFLAGS(intf, ld, flags, cfg)	\

	rvu_write64(rvu, blkaddr,	\

		    NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, flags), cfg)



enum NPC_LID_E {

	NPC_LID_LA = 0,

	NPC_LID_LB,

drivers/net/ethernet/marvell/octeontx2/af/rvu.c

+5 −0
Original line number Diff line number Diff line
@@ -68,6 +68,7 @@ static void rvu_setup_hw_capabilities(struct rvu *rvu) 
	hw->cap.nix_tx_link_bp = true;

	hw->cap.nix_rx_multicast = true;

	hw->cap.nix_shaper_toggle_wait = false;

	hw->cap.npc_hash_extract = false;

	hw->rvu = rvu;



	if (is_rvu_pre_96xx_C0(rvu)) {
@@ -85,6 +86,9 @@ static void rvu_setup_hw_capabilities(struct rvu *rvu) 


	if (!is_rvu_otx2(rvu))

		hw->cap.per_pf_mbox_regs = true;



	if (is_rvu_npc_hash_extract_en(rvu))

		hw->cap.npc_hash_extract = true;

}



/* Poll a RVU block's register 'offset', for a 'zero'
@@ -1991,6 +1995,7 @@ int rvu_mbox_handler_get_hw_cap(struct rvu *rvu, struct msg_req *req, 


	rsp->nix_fixed_txschq_mapping = hw->cap.nix_fixed_txschq_mapping;

	rsp->nix_shaping = hw->cap.nix_shaping;

	rsp->npc_hash_extract = hw->cap.npc_hash_extract;



	return 0;

}

drivers/net/ethernet/marvell/octeontx2/af/rvu.h

+13 −0
Original line number Diff line number Diff line
@@ -338,6 +338,7 @@ struct hw_cap { 
	bool	per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */

	bool	programmable_chans; /* Channels programmable ? */

	bool	ipolicer;

	bool	npc_hash_extract; /* Hash extract enabled ? */

};



struct rvu_hwinfo {
@@ -419,6 +420,7 @@ struct npc_kpu_profile_adapter { 
	const struct npc_kpu_profile_action	*ikpu; /* array[pkinds] */

	const struct npc_kpu_profile	*kpu; /* array[kpus] */

	struct npc_mcam_kex		*mkex;

	struct npc_mcam_kex_hash	*mkex_hash;

	bool				custom;

	size_t				pkinds;

	size_t				kpus;
@@ -575,6 +577,17 @@ static inline bool is_rvu_otx2(struct rvu *rvu) 
		midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO);

}



static inline bool is_rvu_npc_hash_extract_en(struct rvu *rvu)

{

	u64 npc_const3;



	npc_const3 = rvu_read64(rvu, BLKADDR_NPC, NPC_AF_CONST3);

	if (!(npc_const3 & BIT_ULL(62)))

		return false;



	return true;

}



static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid,

				   u8 lmacid, u8 chan)

{