powercap: intel_rapl: Add support for lock bit per Power Limit

mainline inclusion
from mainline-v6.5-rc1
commit f442bd27
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I92135

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f442bd2742174eed6993315ec621275df13f311d



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With RAPL MSR/MMIO Interface, each RAPL domain has one Power Limit
register. Each Power Limit register has one lock bit which tells the OS
if the power limit register can be used or not.
Depending on the number of power limits supported by the power limit
register, the lock bit may apply to one or more power limits.

With RAPL TPMI Interface, each RAPL domain has multiple Power Limits,
and each Power Limit has its own register, with a lock bit.

To handle this, introduce support for lock bit per Power Limit.

For existing RAPL MSR/MMIO Interfaces, the lock bit in the Power Limit
register applies to all the Power Limits controlled by this register.

Remove the per domain DOMAIN_STATE_BIOS_LOCKED flag at the same time
because it can be replaced by the per Power Limit lock.

No functional change intended.

Intel-SIG: commit f442bd27 powercap: intel_rapl: Add support for lock bit per Power Limit.
Backport Intel RAPL driver support on TPMI.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Tested-by: Wang Wendy <wendy.wang@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
[ Xiaolong Wang: amend commit log ]
Signed-off-by: Xiaolong Wang <xiaolong.wang@intel.com>