Commit a94ac342 authored by Haoyue Xu's avatar Haoyue Xu Committed by Zheng Zengkai
Browse files

RDMA/hns: Refactor the abnormal interrupt handler function 

mainline inclusion
from mainline-for-next
commit 75e4e716
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I5IZO5
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git/commit/?id=75e4e716f7089558fda4ddc660fa8dbdec4eb1d3

----------------------------------------------------------------------

Use a single function to handle the same kind of abnormal interrupts.

Link: https://lore.kernel.org/r/20220714134353.16700-5-liangwenpeng@huawei.com


Signed-off-by: default avatarHaoyue Xu <xuhaoyue1@hisilicon.com>
Signed-off-by: default avatarWenpeng Liang <liangwenpeng@huawei.com>
Signed-off-by: default avatarLeon Romanovsky <leon@kernel.org>
Signed-off-by: default avatarZhengfeng Luo <luozhengfeng@h-partners.com>
Reviewed-by: default avatarYangyang Li <liyangyang20@huawei.com>
Reviewed-by: default avatarYue Haibing <yuehaibing@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parent 04adfd7f

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

+23 −12
Original line number Diff line number Diff line
@@ -5628,24 +5628,19 @@ static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) 
	return IRQ_RETVAL(int_work);

}



static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)

static irqreturn_t abnormal_interrupt_basic(struct hns_roce_dev *hr_dev,

					    u32 int_st)

{

	struct hns_roce_dev *hr_dev = dev_id;

	struct device *dev = hr_dev->dev;

	struct pci_dev *pdev = hr_dev->pci_dev;

	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);

	const struct hnae3_ae_ops *ops = ae_dev->ops;

	irqreturn_t int_work = IRQ_NONE;

	u32 int_st;

	u32 int_en;



	/* Abnormal interrupt */

	int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG);

	int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG);



	if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) {

		struct pci_dev *pdev = hr_dev->pci_dev;

		struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);

		const struct hnae3_ae_ops *ops = ae_dev->ops;



		dev_err(dev, "AEQ overflow!\n");

		dev_err(hr_dev->dev, "AEQ overflow!\n");



		roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG,

			   1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S);
@@ -5662,12 +5657,28 @@ static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) 


		int_work = IRQ_HANDLED;

	} else {

		dev_err(dev, "There is no abnormal irq found!\n");

		dev_err(hr_dev->dev, "there is no basic abn irq found.\n");

	}



	return IRQ_RETVAL(int_work);

}



static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)

{

	struct hns_roce_dev *hr_dev = dev_id;

	irqreturn_t int_work = IRQ_NONE;

	u32 int_st;



	int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG);



	if (int_st)

		int_work = abnormal_interrupt_basic(hr_dev, int_st);

	else

		dev_err(hr_dev->dev, "there is no abnormal irq found.\n");



	return IRQ_RETVAL(int_work);

}



static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev,

					int eq_num, u32 enable_flag)

{