Commit a935601e authored by Bhupesh Sharma's avatar Bhupesh Sharma Committed by Bjorn Helgaas
Browse files

PCI: qcom: Add SM8150 SoC support 

The PCIe IP (rev 1.5.0) on SM8150 SoC is similar to the one used on
SM8250. Add SM8150 support, reusing the members of ops_1_9_0.

Link: https://lore.kernel.org/r/20220326060810.1797516-3-bhupesh.sharma@linaro.org


Signed-off-by: default avatarBhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Cc: Vinod Koul <vkoul@kernel.org>
parent a6e25b39

drivers/pci/controller/dwc/pcie-qcom.c

+8 −0
Original line number Diff line number Diff line
@@ -1523,6 +1523,13 @@ static const struct qcom_pcie_cfg sdm845_cfg = { 
	.has_tbu_clk = true,

};



static const struct qcom_pcie_cfg sm8150_cfg = {

	/* sm8150 has qcom IP rev 1.5.0. However 1.5.0 ops are same as

	 * 1.9.0, so reuse the same.

	 */

	.ops = &ops_1_9_0,

};



static const struct qcom_pcie_cfg sm8250_cfg = {

	.ops = &ops_1_9_0,

	.has_tbu_clk = true,
@@ -1655,6 +1662,7 @@ static const struct of_device_id qcom_pcie_match[] = { 
	{ .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg },

	{ .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg },

	{ .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },

	{ .compatible = "qcom,pcie-sm8150", .data = &sm8150_cfg },

	{ .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },

	{ .compatible = "qcom,pcie-sc8180x", .data = &sm8250_cfg },

	{ .compatible = "qcom,pcie-sm8450-pcie0", .data = &sm8450_pcie0_cfg },