Commit a90f2115 authored by Ben Greear's avatar Ben Greear Committed by Felix Fietkau
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mt76: mt7915: add more MIB registers 



Add register definitions and read & accumulate them in
the mib polling logic.  Note that some registers should not
be read since firmware is already reading them.  If driver
reads those, they will be cleared-on-read, and so the firmware
stats will be incorrect.

For these 'do-not-read' stats, add them to the registers definition
so that other developers can be aware of these constraints, but do
not actually read them in the driver.

Signed-off-by: default avatarBen Greear <greearb@candelatech.com>
Signed-off-by: default avatarFelix Fietkau <nbd@nbd.name>
parent 016f2040

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

+65 −0
Original line number Diff line number Diff line
@@ -1927,6 +1927,71 @@ mt7915_mac_update_stats(struct mt7915_phy *phy) 


	mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(ext_phy),

					   MT_MIB_SDR3_FCS_ERR_MASK);



	cnt = mt76_rr(dev, MT_MIB_SDR4(ext_phy));

	mib->rx_fifo_full_cnt += FIELD_GET(MT_MIB_SDR4_RX_FIFO_FULL_MASK, cnt);



	cnt = mt76_rr(dev, MT_MIB_SDR5(ext_phy));

	mib->rx_mpdu_cnt += cnt;



	cnt = mt76_rr(dev, MT_MIB_SDR6(ext_phy));

	mib->channel_idle_cnt += FIELD_GET(MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK, cnt);



	cnt = mt76_rr(dev, MT_MIB_SDR7(ext_phy));

	mib->rx_vector_mismatch_cnt += FIELD_GET(MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK, cnt);



	cnt = mt76_rr(dev, MT_MIB_SDR8(ext_phy));

	mib->rx_delimiter_fail_cnt += FIELD_GET(MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK, cnt);



	cnt = mt76_rr(dev, MT_MIB_SDR11(ext_phy));

	mib->rx_len_mismatch_cnt += FIELD_GET(MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK, cnt);



	cnt = mt76_rr(dev, MT_MIB_SDR12(ext_phy));

	mib->tx_ampdu_cnt += cnt;



	cnt = mt76_rr(dev, MT_MIB_SDR13(ext_phy));

	mib->tx_stop_q_empty_cnt += FIELD_GET(MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK, cnt);



	cnt = mt76_rr(dev, MT_MIB_SDR14(ext_phy));

	mib->tx_mpdu_attempts_cnt += FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK, cnt);



	cnt = mt76_rr(dev, MT_MIB_SDR15(ext_phy));

	mib->tx_mpdu_success_cnt += FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK, cnt);



	cnt = mt76_rr(dev, MT_MIB_SDR22(ext_phy));

	mib->rx_ampdu_cnt += cnt;



	cnt = mt76_rr(dev, MT_MIB_SDR23(ext_phy));

	mib->rx_ampdu_bytes_cnt += cnt;



	cnt = mt76_rr(dev, MT_MIB_SDR24(ext_phy));

	mib->rx_ampdu_valid_subframe_cnt += FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK, cnt);



	cnt = mt76_rr(dev, MT_MIB_SDR25(ext_phy));

	mib->rx_ampdu_valid_subframe_bytes_cnt += cnt;



	cnt = mt76_rr(dev, MT_MIB_SDR27(ext_phy));

	mib->tx_rwp_fail_cnt += FIELD_GET(MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK, cnt);



	cnt = mt76_rr(dev, MT_MIB_SDR28(ext_phy));

	mib->tx_rwp_need_cnt += FIELD_GET(MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK, cnt);



	cnt = mt76_rr(dev, MT_MIB_SDR29(ext_phy));

	mib->rx_pfdrop_cnt += FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK, cnt);



	cnt = mt76_rr(dev, MT_MIB_SDR30(ext_phy));

	mib->rx_vec_queue_overflow_drop_cnt +=

		FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK, cnt);



	cnt = mt76_rr(dev, MT_MIB_SDR31(ext_phy));

	mib->rx_ba_cnt += cnt;



	cnt = mt76_rr(dev, MT_MIB_SDR32(ext_phy));

	mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT_MASK, cnt);



	cnt = mt76_rr(dev, MT_MIB_SDR33(ext_phy));

	mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR33_TX_PKT_IBF_CNT_MASK, cnt);



	cnt = mt76_rr(dev, MT_MIB_SDR34(ext_phy));

	mib->tx_bf_cnt += FIELD_GET(MT_MIB_MU_BF_TX_CNT, cnt);

drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h

+24 −1
Original line number Diff line number Diff line
@@ -130,7 +130,30 @@ struct mib_stats { 
	u32 tx_bf_fb_cpl_cnt;

	u32 tx_bf_fb_trig_cnt;



	/* Add more stats here, updated from mac_update_stats */

	u32 tx_ampdu_cnt;

	u32 tx_stop_q_empty_cnt;

	u32 tx_mpdu_attempts_cnt;

	u32 tx_mpdu_success_cnt;

	u32 tx_pkt_ebf_cnt;

	u32 tx_pkt_ibf_cnt;



	u32 tx_rwp_fail_cnt;

	u32 tx_rwp_need_cnt;



	/* rx stats */

	u32 rx_fifo_full_cnt;

	u32 channel_idle_cnt;

	u32 rx_vector_mismatch_cnt;

	u32 rx_delimiter_fail_cnt;

	u32 rx_len_mismatch_cnt;

	u32 rx_mpdu_cnt;

	u32 rx_ampdu_cnt;

	u32 rx_ampdu_bytes_cnt;

	u32 rx_ampdu_valid_subframe_cnt;

	u32 rx_ampdu_valid_subframe_bytes_cnt;

	u32 rx_pfdrop_cnt;

	u32 rx_vec_queue_overflow_drop_cnt;

	u32 rx_ba_cnt;

};



struct mt7915_hif {

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

+105 −0
Original line number Diff line number Diff line
@@ -139,15 +139,120 @@ 
#define MT_LPON_TCR_SW_READ		GENMASK(1, 0)



/* MIB: band 0(0x24800), band 1(0xa4800) */

/* These counters are (mostly?) clear-on-read.  So, some should not

 * be read at all in case firmware is already reading them.  These

 * are commented with 'DNR' below.  The DNR stats will be read by querying

 * the firmware API for the appropriate message.  For counters the driver

 * does read, the driver should accumulate the counters.

 */

#define MT_WF_MIB_BASE(_band)		((_band) ? 0xa4800 : 0x24800)

#define MT_WF_MIB(_band, ofs)		(MT_WF_MIB_BASE(_band) + (ofs))



#define MT_MIB_SDR0(_band)		MT_WF_MIB(_band, 0x010)

#define MT_MIB_SDR0_BERACON_TX_CNT_MASK	GENMASK(15, 0)



#define MT_MIB_SDR3(_band)		MT_WF_MIB(_band, 0x014)

#define MT_MIB_SDR3_FCS_ERR_MASK	GENMASK(15, 0)



#define MT_MIB_SDR4(_band)		MT_WF_MIB(_band, 0x018)

#define MT_MIB_SDR4_RX_FIFO_FULL_MASK	GENMASK(15, 0)



/* rx mpdu counter, full 32 bits */

#define MT_MIB_SDR5(_band)		MT_WF_MIB(_band, 0x01c)



#define MT_MIB_SDR6(_band)		MT_WF_MIB(_band, 0x020)

#define MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK	GENMASK(15, 0)



#define MT_MIB_SDR7(_band)		MT_WF_MIB(_band, 0x024)

#define MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK	GENMASK(15, 0)



#define MT_MIB_SDR8(_band)		MT_WF_MIB(_band, 0x028)

#define MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK	GENMASK(15, 0)



/* aka CCA_NAV_TX_TIME */

#define MT_MIB_SDR9_DNR(_band)		MT_WF_MIB(_band, 0x02c)

#define MT_MIB_SDR9_CCA_BUSY_TIME_MASK	GENMASK(23, 0)



#define MT_MIB_SDR10_DNR(_band)		MT_WF_MIB(_band, 0x030)

#define MT_MIB_SDR10_MRDY_COUNT_MASK	GENMASK(25, 0)



#define MT_MIB_SDR11(_band)		MT_WF_MIB(_band, 0x034)

#define MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK	GENMASK(15, 0)



/* tx ampdu cnt, full 32 bits */

#define MT_MIB_SDR12(_band)		MT_WF_MIB(_band, 0x038)



#define MT_MIB_SDR13(_band)		MT_WF_MIB(_band, 0x03c)

#define MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK	GENMASK(15, 0)



/* counts all mpdus in ampdu, regardless of success */

#define MT_MIB_SDR14(_band)		MT_WF_MIB(_band, 0x040)

#define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK	GENMASK(23, 0)



/* counts all successfully tx'd mpdus in ampdu */

#define MT_MIB_SDR15(_band)		MT_WF_MIB(_band, 0x044)

#define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK	GENMASK(23, 0)



/* in units of 'us' */

#define MT_MIB_SDR16_DNR(_band)		MT_WF_MIB(_band, 0x048)

#define MT_MIB_SDR16_PRIMARY_CCA_BUSY_TIME_MASK	GENMASK(23, 0)



#define MT_MIB_SDR17_DNR(_band)		MT_WF_MIB(_band, 0x04c)

#define MT_MIB_SDR17_SECONDARY_CCA_BUSY_TIME_MASK	GENMASK(23, 0)



#define MT_MIB_SDR18(_band)		MT_WF_MIB(_band, 0x050)

#define MT_MIB_SDR18_PRIMARY_ENERGY_DETECT_TIME_MASK	GENMASK(23, 0)



/* units are us */

#define MT_MIB_SDR19_DNR(_band)		MT_WF_MIB(_band, 0x054)

#define MT_MIB_SDR19_CCK_MDRDY_TIME_MASK	GENMASK(23, 0)



#define MT_MIB_SDR20_DNR(_band)		MT_WF_MIB(_band, 0x058)

#define MT_MIB_SDR20_OFDM_VHT_MDRDY_TIME_MASK	GENMASK(23, 0)



#define MT_MIB_SDR21_DNR(_band)		MT_WF_MIB(_band, 0x05c)

#define MT_MIB_SDR20_GREEN_MDRDY_TIME_MASK	GENMASK(23, 0)



/* rx ampdu count, 32-bit */

#define MT_MIB_SDR22(_band)		MT_WF_MIB(_band, 0x060)



/* rx ampdu bytes count, 32-bit */

#define MT_MIB_SDR23(_band)		MT_WF_MIB(_band, 0x064)



/* rx ampdu valid subframe count */

#define MT_MIB_SDR24(_band)		MT_WF_MIB(_band, 0x068)

#define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK	GENMASK(23, 0)



/* rx ampdu valid subframe bytes count, 32bits */

#define MT_MIB_SDR25(_band)		MT_WF_MIB(_band, 0x06c)



/* remaining windows protected stats */

#define MT_MIB_SDR27(_band)		MT_WF_MIB(_band, 0x074)

#define MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK	GENMASK(15, 0)



#define MT_MIB_SDR28(_band)		MT_WF_MIB(_band, 0x078)

#define MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK	GENMASK(15, 0)



#define MT_MIB_SDR29(_band)		MT_WF_MIB(_band, 0x07c)

#define MT_MIB_SDR29_RX_PFDROP_CNT_MASK	GENMASK(7, 0)



#define MT_MIB_SDR30(_band)		MT_WF_MIB(_band, 0x080)

#define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK	GENMASK(15, 0)



/* rx blockack count, 32 bits */

#define MT_MIB_SDR31(_band)		MT_WF_MIB(_band, 0x084)



#define MT_MIB_SDR32(_band)		MT_WF_MIB(_band, 0x088)

#define MT_MIB_SDR32_TX_PKT_EBF_CNT_MASK	GENMASK(15, 0)



#define MT_MIB_SDR33(_band)		MT_WF_MIB(_band, 0x08c)

#define MT_MIB_SDR33_TX_PKT_IBF_CNT_MASK	GENMASK(15, 0)



#define MT_MIB_SDR34(_band)		MT_WF_MIB(_band, 0x090)

#define MT_MIB_MU_BF_TX_CNT		GENMASK(15, 0)



/* 36, 37 both DNR */



#define MT_MIB_DR8(_band)		MT_WF_MIB(_band, 0x0c0)

#define MT_MIB_DR9(_band)		MT_WF_MIB(_band, 0x0c4)

#define MT_MIB_DR11(_band)		MT_WF_MIB(_band, 0x0cc)