Commit a8e380fd authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
Browse files

drm/amd/display: Update bounding box for DCN3.1 



[Why & How]
We're missing a default value for dram_channel_width_bytes in the
DCN3.1 SOC bounding box and we don't currently have the interface in
place to query the actual value from VBIOS.

Put in a hardcoded default until we have the interface in place.

Reviewed-by: default avatarEric Yang <eric.yang2@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b0364fa4

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c

+1 −0
Original line number Diff line number Diff line
@@ -220,6 +220,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = { 
	.sr_exit_z8_time_us = 402.0,

	.sr_enter_plus_exit_z8_time_us = 520.0,

	.writeback_latency_us = 12.0,

	.dram_channel_width_bytes = 4,

	.round_trip_ping_latency_dcfclk_cycles = 106,

	.urgent_latency_pixel_data_only_us = 4.0,

	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,