Commit a8caaa23 authored by Mark Brown's avatar Mark Brown Committed by Catalin Marinas
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arm64/sme: Document boot requirements for SME 



Document our requirements for initialisation of the Scalable Matrix
Extension (SME) at kernel start. While we do have the ability to handle
mismatched vector lengths we will reject any late CPUs that can't support
the minimum set we determine at boot so for clarity we document a
requirement that all CPUs make the same vector length available.

Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20210720204220.22951-1-broonie@kernel.org


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 2806556c

Documentation/arm64/booting.rst

+22 −0
Original line number Diff line number Diff line
@@ -311,6 +311,28 @@ Before jumping into the kernel, the following conditions must be met: 
    - ZCR_EL2.LEN must be initialised to the same value for all CPUs the

      kernel will execute on.



  For CPUs with the Scalable Matrix Extension (FEAT_SME):



  - If EL3 is present:



    - CPTR_EL3.ESM (bit 12) must be initialised to 0b1.



    - SCR_EL3.EnTP2 (bit 41) must be initialised to 0b1.



    - SMCR_EL3.LEN must be initialised to the same value for all CPUs the

      kernel will execute on.



 - If the kernel is entered at EL1 and EL2 is present:



    - CPTR_EL2.TSM (bit 12) must be initialised to 0b0.



    - CPTR_EL2.SMEN (bits 25:24) must be initialised to 0b11.



    - SCTLR_EL2.EnTP2 (bit 60) must be initialised to 0b1.



    - SMCR_EL2.LEN must be initialised to the same value for all CPUs the

      kernel will execute on.



The requirements described above for CPU mode, caches, MMUs, architected

timers, coherency and system registers apply to all CPUs.  All CPUs must

enter the kernel in the same exception level.  Where the values documented