Unverified Commit a8c371f0 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'v5.14-next-soc' of... 

Merge tag 'v5.14-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers

pm-domains:
- correct mask define if used for update on TOPAXI bus
- mt8173: enable regulator befor turning on MFG_ASYNC

mmsys:
- add a mask property to the routing information
- add support for MT8365
- add UFOE routing for MT8173

* tag 'v5.14-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  soc: mediatek: mmsys: Fix missing UFOE component in mt8173 table routing
  soc: mediatek: mmsys: add MT8365 support
  soc: mmsys: mediatek: add mask to mmsys routes
  soc: mediatek: pm-domains: Add domain_supply cap for mfg_async PD
  soc: mediatek: pm-domains: Use correct mask for bus_prot_clr

Link: https://lore.kernel.org/r/49fc7bef-20db-b98c-9437-dd9e4d00e870@gmail.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents a41461b6 25423731

drivers/soc/mediatek/mt8173-pm-domains.h

+1 −0
Original line number Diff line number Diff line
@@ -71,6 +71,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { 
		.ctl_offs = SPM_MFG_ASYNC_PWR_CON,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = 0,

		.caps = MTK_SCPD_DOMAIN_SUPPLY,

	},

	[MT8173_POWER_DOMAIN_MFG_2D] = {

		.name = "mfg_2d",

drivers/soc/mediatek/mt8183-mmsys.h

+14 −7
Original line number Diff line number Diff line
@@ -28,25 +28,32 @@ 
static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {

	{

		DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,

		MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L

		MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L,

		MT8183_OVL0_MOUT_EN_OVL0_2L

	}, {

		DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,

		MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0

		MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0,

		MT8183_OVL0_2L_MOUT_EN_DISP_PATH0

	}, {

		DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1,

		MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1

		MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,

		MT8183_OVL1_2L_MOUT_EN_RDMA1

	}, {

		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,

		MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0

		MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,

		MT8183_DITHER0_MOUT_IN_DSI0

	}, {

		DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,

		MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L

		MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L,

		MT8183_DISP_PATH0_SEL_IN_OVL0_2L

	}, {

		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,

		MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1

		MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1,

		MT8183_DPI0_SEL_IN_RDMA1

	}, {

		DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,

		MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0

		MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0,

		MT8183_RDMA0_SOUT_COLOR0

	}

};

drivers/soc/mediatek/mt8365-mmsys.h

0 → 100644
+60 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */



#ifndef __SOC_MEDIATEK_MT8365_MMSYS_H

#define __SOC_MEDIATEK_MT8365_MMSYS_H



#define MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0xf3c

#define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL	0xf4c

#define MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN	0xf50

#define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN	0xf54

#define MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN	0xf60

#define MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0xf64

#define MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN		0xf68



#define MT8365_RDMA0_SOUT_COLOR0			0x1

#define MT8365_DITHER_MOUT_EN_DSI0			0x1

#define MT8365_DSI0_SEL_IN_DITHER			0x1

#define MT8365_RDMA0_SEL_IN_OVL0			0x0

#define MT8365_RDMA0_RSZ0_SEL_IN_RDMA0			0x0

#define MT8365_DISP_COLOR_SEL_IN_COLOR0			0x0

#define MT8365_OVL0_MOUT_PATH0_SEL			BIT(0)



static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {

	{

		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,

		MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,

		MT8365_OVL0_MOUT_PATH0_SEL, MT8365_OVL0_MOUT_PATH0_SEL

	},

	{

		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,

		MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN,

		MT8365_RDMA0_SEL_IN_OVL0, MT8365_RDMA0_SEL_IN_OVL0

	},

	{

		DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,

		MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL,

		MT8365_RDMA0_SOUT_COLOR0, MT8365_RDMA0_SOUT_COLOR0

	},

	{

		DDP_COMPONENT_COLOR0, DDP_COMPONENT_CCORR,

		MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,

		MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0

	},

	{

		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,

		MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,

		MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0

	},

	{

		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,

		MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,

		MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER

	},

	{

		DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,

		MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,

		MT8365_RDMA0_RSZ0_SEL_IN_RDMA0, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0

	},

};



#endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */

drivers/soc/mediatek/mtk-mmsys.c

+16 −2
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include "mtk-mmsys.h"

#include "mt8167-mmsys.h"

#include "mt8183-mmsys.h"

#include "mt8365-mmsys.h"



static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {

	.clk_driver = "clk-mt2701-mm",
@@ -52,6 +53,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { 
	.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),

};



static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {

	.clk_driver = "clk-mt8365-mm",

	.routes = mt8365_mmsys_routing_table,

	.num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),

};



struct mtk_mmsys {

	void __iomem *regs;

	const struct mtk_mmsys_driver_data *data;
@@ -68,7 +75,9 @@ void mtk_mmsys_ddp_connect(struct device *dev, 


	for (i = 0; i < mmsys->data->num_routes; i++)

		if (cur == routes[i].from_comp && next == routes[i].to_comp) {

			reg = readl_relaxed(mmsys->regs + routes[i].addr) | routes[i].val;

			reg = readl_relaxed(mmsys->regs + routes[i].addr);

			reg &= ~routes[i].mask;

			reg |= routes[i].val;

			writel_relaxed(reg, mmsys->regs + routes[i].addr);

		}

}
@@ -85,7 +94,8 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, 


	for (i = 0; i < mmsys->data->num_routes; i++)

		if (cur == routes[i].from_comp && next == routes[i].to_comp) {

			reg = readl_relaxed(mmsys->regs + routes[i].addr) & ~routes[i].val;

			reg = readl_relaxed(mmsys->regs + routes[i].addr);

			reg &= ~routes[i].mask;

			writel_relaxed(reg, mmsys->regs + routes[i].addr);

		}

}
@@ -157,6 +167,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = { 
		.compatible = "mediatek,mt8183-mmsys",

		.data = &mt8183_mmsys_driver_data,

	},

	{

		.compatible = "mediatek,mt8365-mmsys",

		.data = &mt8365_mmsys_driver_data,

	},

	{ }

};

drivers/soc/mediatek/mtk-mmsys.h

+97 −40
Original line number Diff line number Diff line
@@ -35,41 +35,54 @@ 
#define RDMA0_SOUT_DSI1				0x1

#define RDMA0_SOUT_DSI2				0x4

#define RDMA0_SOUT_DSI3				0x5

#define RDMA0_SOUT_MASK				0x7

#define RDMA1_SOUT_DPI0				0x2

#define RDMA1_SOUT_DPI1				0x3

#define RDMA1_SOUT_DSI1				0x1

#define RDMA1_SOUT_DSI2				0x4

#define RDMA1_SOUT_DSI3				0x5

#define RDMA1_SOUT_MASK				0x7

#define RDMA2_SOUT_DPI0				0x2

#define RDMA2_SOUT_DPI1				0x3

#define RDMA2_SOUT_DSI1				0x1

#define RDMA2_SOUT_DSI2				0x4

#define RDMA2_SOUT_DSI3				0x5

#define RDMA2_SOUT_MASK				0x7

#define DPI0_SEL_IN_RDMA1			0x1

#define DPI0_SEL_IN_RDMA2			0x3

#define DPI0_SEL_IN_MASK			0x3

#define DPI1_SEL_IN_RDMA1			(0x1 << 8)

#define DPI1_SEL_IN_RDMA2			(0x3 << 8)

#define DPI1_SEL_IN_MASK			(0x3 << 8)

#define DSI0_SEL_IN_RDMA1			0x1

#define DSI0_SEL_IN_RDMA2			0x4

#define DSI0_SEL_IN_MASK			0x7

#define DSI1_SEL_IN_RDMA1			0x1

#define DSI1_SEL_IN_RDMA2			0x4

#define DSI1_SEL_IN_MASK			0x7

#define DSI2_SEL_IN_RDMA1			(0x1 << 16)

#define DSI2_SEL_IN_RDMA2			(0x4 << 16)

#define DSI2_SEL_IN_MASK			(0x7 << 16)

#define DSI3_SEL_IN_RDMA1			(0x1 << 16)

#define DSI3_SEL_IN_RDMA2			(0x4 << 16)

#define DSI3_SEL_IN_MASK			(0x7 << 16)

#define COLOR1_SEL_IN_OVL1			0x1



#define OVL_MOUT_EN_RDMA			0x1

#define BLS_TO_DSI_RDMA1_TO_DPI1		0x8

#define BLS_TO_DPI_RDMA1_TO_DSI			0x2

#define BLS_RDMA1_DSI_DPI_MASK			0xf

#define DSI_SEL_IN_BLS				0x0

#define DPI_SEL_IN_BLS				0x0

#define DPI_SEL_IN_MASK				0x1

#define DSI_SEL_IN_RDMA				0x1

#define DSI_SEL_IN_MASK				0x1



struct mtk_mmsys_routes {

	u32 from_comp;

	u32 to_comp;

	u32 addr;

	u32 mask;

	u32 val;

};
@@ -91,124 +104,168 @@ struct mtk_mmsys_driver_data { 
static const struct mtk_mmsys_routes mmsys_default_routing_table[] = {

	{

		DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,

		DISP_REG_CONFIG_OUT_SEL, BLS_TO_DSI_RDMA1_TO_DPI1

		DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,

		BLS_TO_DSI_RDMA1_TO_DPI1

	}, {

		DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,

		DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_BLS

		DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,

		DSI_SEL_IN_BLS

	}, {

		DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,

		DISP_REG_CONFIG_OUT_SEL, BLS_TO_DPI_RDMA1_TO_DSI

		DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,

		BLS_TO_DPI_RDMA1_TO_DSI

	}, {

		DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,

		DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_RDMA

		DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,

		DSI_SEL_IN_RDMA

	}, {

		DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,

		DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_BLS

		DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_MASK,

		DPI_SEL_IN_BLS

	}, {

		DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1,

		DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1

		DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1,

		GAMMA_MOUT_EN_RDMA1

	}, {

		DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0,

		DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0

		DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0,

		OD_MOUT_EN_RDMA0

	}, {

		DDP_COMPONENT_OD1, DDP_COMPONENT_RDMA1,

		DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1

		DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1,

		OD1_MOUT_EN_RDMA1

	}, {

		DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,

		DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0

		DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,

		OVL0_MOUT_EN_COLOR0

	}, {

		DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,

		DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0

		DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,

		COLOR0_SEL_IN_OVL0

	}, {

		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,

		DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA

		DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA,

		OVL_MOUT_EN_RDMA

	}, {

		DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,

		DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1

		DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1,

		OVL1_MOUT_EN_COLOR1

	}, {

		DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,

		DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1

		DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1,

		COLOR1_SEL_IN_OVL1

	}, {

		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI0,

		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DPI0

		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,

		RDMA0_SOUT_DPI0

	}, {

		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI1,

		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DPI1

		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,

		RDMA0_SOUT_DPI1

	}, {

		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI1,

		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DSI1

		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,

		RDMA0_SOUT_DSI1

	}, {

		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI2,

		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DSI2

		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,

		RDMA0_SOUT_DSI2

	}, {

		DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI3,

		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DSI3

		DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,

		RDMA0_SOUT_DSI3

	}, {

		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,

		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DPI0

		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,

		RDMA1_SOUT_DPI0

	}, {

		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,

		DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_RDMA1

		DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,

		DPI0_SEL_IN_RDMA1

	}, {

		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,

		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DPI1

		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,

		RDMA1_SOUT_DPI1

	}, {

		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,

		DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_RDMA1

		DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,

		DPI1_SEL_IN_RDMA1

	}, {

		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI0,

		DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_RDMA1

		DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,

		DSI0_SEL_IN_RDMA1

	}, {

		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,

		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DSI1

		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,

		RDMA1_SOUT_DSI1

	}, {

		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,

		DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_RDMA1

		DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,

		DSI1_SEL_IN_RDMA1

	}, {

		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,

		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DSI2

		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,

		RDMA1_SOUT_DSI2

	}, {

		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,

		DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_RDMA1

		DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,

		DSI2_SEL_IN_RDMA1

	}, {

		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,

		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DSI3

		DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,

		RDMA1_SOUT_DSI3

	}, {

		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,

		DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_RDMA1

		DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,

		DSI3_SEL_IN_RDMA1

	}, {

		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,

		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DPI0

		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,

		RDMA2_SOUT_DPI0

	}, {

		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,

		DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_RDMA2

		DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,

		DPI0_SEL_IN_RDMA2

	}, {

		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,

		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DPI1

		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,

		RDMA2_SOUT_DPI1

	}, {

		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,

		DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_RDMA2

		DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,

		DPI1_SEL_IN_RDMA2

	}, {

		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI0,

		DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_RDMA2

		DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,

		DSI0_SEL_IN_RDMA2

	}, {

		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,

		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DSI1

		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,

		RDMA2_SOUT_DSI1

	}, {

		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,

		DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_RDMA2

		DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,

		DSI1_SEL_IN_RDMA2

	}, {

		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,

		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DSI2

		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,

		RDMA2_SOUT_DSI2

	}, {

		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,

		DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_RDMA2

		DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,

		DSI2_SEL_IN_RDMA2

	}, {

		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,

		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DSI3

		DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,

		RDMA2_SOUT_DSI3

	}, {

		DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,

		DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_RDMA2

		DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,

		DSI3_SEL_IN_RDMA2

	}, {

		DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,

		DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, UFOE_MOUT_EN_DSI0,

		UFOE_MOUT_EN_DSI0

	}

};