Commit a8bf7164 authored by Krunoslav Kovac's avatar Krunoslav Kovac Committed by Alex Deucher
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drm/amd/display: Internal refactoring to abstract color caps 



[Why&How]
modules/color calculates various colour operations which are translated
to abstracted HW. DCE 5-12 had almost no important changes, but
starting with DCN1, every new generation comes with fairly major
differences in color pipeline.
We would hack it with some DCN checks, but a better approach is to
abstract color pipe capabilities so modules/DM can decide mapping to
HW block based on logical capabilities,

Signed-off-by: default avatarKrunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: default avatarAric Cyr <Aric.Cyr@amd.com>
Acked-by: default avatarAnthony Koo <Anthony.Koo@amd.com>
Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4b0e95d1

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

+4 −3
Original line number Diff line number Diff line
@@ -239,7 +239,8 @@ static int __set_output_tf(struct dc_transfer_func *func, 
		 * instead to simulate this.

		 */

		gamma->type = GAMMA_CUSTOM;

		res = mod_color_calculate_degamma_params(func, gamma, true);

		res = mod_color_calculate_degamma_params(NULL, func,

							gamma, true);

	} else {

		/*

		 * Assume sRGB. The actual mapping will depend on whether the
@@ -271,7 +272,7 @@ static int __set_input_tf(struct dc_transfer_func *func, 


	__drm_lut_to_dc_gamma(lut, gamma, false);



	res = mod_color_calculate_degamma_params(func, gamma, true);

	res = mod_color_calculate_degamma_params(NULL, func, gamma, true);

	dc_gamma_release(&gamma);



	return res ? 0 : -ENOMEM;
@@ -485,7 +486,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 
		dc_plane_state->in_transfer_func->tf = tf;



		if (tf != TRANSFER_FUNCTION_SRGB &&

		    !mod_color_calculate_degamma_params(

		    !mod_color_calculate_degamma_params(NULL,

			    dc_plane_state->in_transfer_func, NULL, false))

			return -ENOMEM;

	} else {

drivers/gpu/drm/amd/display/dc/dc.h

+44 −1
Original line number Diff line number Diff line
@@ -98,6 +98,49 @@ struct dc_plane_cap { 
	} max_downscale_factor;

};



// Color management caps (DPP and MPC)

struct rom_curve_caps {

	uint16_t srgb : 1;

	uint16_t bt2020 : 1;

	uint16_t gamma2_2 : 1;

	uint16_t pq : 1;

	uint16_t hlg : 1;

};



struct dpp_color_caps {

	uint16_t dcn_arch : 1; // all DCE generations treated the same

	// input lut is different than most LUTs, just plain 256-entry lookup

	uint16_t input_lut_shared : 1; // shared with DGAM

	uint16_t icsc : 1;

	uint16_t dgam_ram : 1;

	uint16_t post_csc : 1; // before gamut remap

	uint16_t gamma_corr : 1;



	// hdr_mult and gamut remap always available in DPP (in that order)

	// 3d lut implies shaper LUT,

	// it may be shared with MPC - check MPC:shared_3d_lut flag

	uint16_t hw_3d_lut : 1;

	uint16_t ogam_ram : 1; // blnd gam

	uint16_t ocsc : 1;

	struct rom_curve_caps dgam_rom_caps;

	struct rom_curve_caps ogam_rom_caps;

};



struct mpc_color_caps {

	uint16_t gamut_remap : 1;

	uint16_t ogam_ram : 1;

	uint16_t ocsc : 1;

	uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT

	uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance



	struct rom_curve_caps ogam_rom_caps;

};



struct dc_color_caps {

	struct dpp_color_caps dpp;

	struct mpc_color_caps mpc;

};



struct dc_caps {

	uint32_t max_streams;

	uint32_t max_links;
@@ -120,9 +163,9 @@ struct dc_caps { 
	bool psp_setup_panel_mode;

	bool extended_aux_timeout_support;

	bool dmcub_support;

	bool hw_3d_lut;

	enum dp_protocol_version max_dp_protocol_version;

	struct dc_plane_cap planes[MAX_PLANES];

	struct dc_color_caps color;

};



struct dc_bug_wa {

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

+34 −0
Original line number Diff line number Diff line
@@ -1384,6 +1384,40 @@ static bool dcn10_resource_construct( 
	/* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */

	dc->caps.force_dp_tps4_for_cp2520 = true;



	/* Color pipeline capabilities */

	dc->caps.color.dpp.dcn_arch = 1;

	dc->caps.color.dpp.input_lut_shared = 1;

	dc->caps.color.dpp.icsc = 1;

	dc->caps.color.dpp.dgam_ram = 1;

	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;

	dc->caps.color.dpp.dgam_rom_caps.pq = 0;

	dc->caps.color.dpp.dgam_rom_caps.hlg = 0;

	dc->caps.color.dpp.post_csc = 0;

	dc->caps.color.dpp.gamma_corr = 0;



	dc->caps.color.dpp.hw_3d_lut = 0;

	dc->caps.color.dpp.ogam_ram = 1; // RGAM on DCN1

	dc->caps.color.dpp.ogam_rom_caps.srgb = 1;

	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 1;

	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

	dc->caps.color.dpp.ogam_rom_caps.pq = 0;

	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

	dc->caps.color.dpp.ocsc = 1;



	/* no post-blend color operations */

	dc->caps.color.mpc.gamut_remap = 0;

	dc->caps.color.mpc.num_3dluts = 0;

	dc->caps.color.mpc.shared_3d_lut = 0;

	dc->caps.color.mpc.ogam_ram = 0;

	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

	dc->caps.color.mpc.ogam_rom_caps.pq = 0;

	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

	dc->caps.color.mpc.ocsc = 0;



	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

		dc->debug = debug_defaults_drv;

	else

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+34 −1
Original line number Diff line number Diff line
@@ -3709,9 +3709,42 @@ static bool dcn20_resource_construct( 
	dc->caps.max_slave_planes = 1;

	dc->caps.post_blend_color_processing = true;

	dc->caps.force_dp_tps4_for_cp2520 = true;

	dc->caps.hw_3d_lut = true;

	dc->caps.extended_aux_timeout_support = true;



	/* Color pipeline capabilities */

	dc->caps.color.dpp.dcn_arch = 1;

	dc->caps.color.dpp.input_lut_shared = 0;

	dc->caps.color.dpp.icsc = 1;

	dc->caps.color.dpp.dgam_ram = 1;

	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;

	dc->caps.color.dpp.dgam_rom_caps.pq = 0;

	dc->caps.color.dpp.dgam_rom_caps.hlg = 0;

	dc->caps.color.dpp.post_csc = 0;

	dc->caps.color.dpp.gamma_corr = 0;



	dc->caps.color.dpp.hw_3d_lut = 1;

	dc->caps.color.dpp.ogam_ram = 1;

	// no OGAM ROM on DCN2, only MPC ROM

	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

	dc->caps.color.dpp.ogam_rom_caps.pq = 0;

	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

	dc->caps.color.dpp.ocsc = 0;



	dc->caps.color.mpc.gamut_remap = 0;

	dc->caps.color.mpc.num_3dluts = 0;

	dc->caps.color.mpc.shared_3d_lut = 0;

	dc->caps.color.mpc.ogam_ram = 1;

	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

	dc->caps.color.mpc.ogam_rom_caps.pq = 0;

	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

	dc->caps.color.mpc.ocsc = 1;



	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) {

		dc->debug = debug_defaults_drv;

	} else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c

+34 −1
Original line number Diff line number Diff line
@@ -1798,7 +1798,6 @@ static bool dcn21_resource_construct( 
	dc->caps.i2c_speed_in_khz = 100;

	dc->caps.max_cursor_size = 256;

	dc->caps.dmdata_alloc_size = 2048;

	dc->caps.hw_3d_lut = true;



	dc->caps.max_slave_planes = 1;

	dc->caps.post_blend_color_processing = true;
@@ -1807,6 +1806,40 @@ static bool dcn21_resource_construct( 
	dc->caps.dmcub_support = true;

	dc->caps.is_apu = true;



	/* Color pipeline capabilities */

	dc->caps.color.dpp.dcn_arch = 1;

	dc->caps.color.dpp.input_lut_shared = 0;

	dc->caps.color.dpp.icsc = 1;

	dc->caps.color.dpp.dgam_ram = 1;

	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;

	dc->caps.color.dpp.dgam_rom_caps.pq = 0;

	dc->caps.color.dpp.dgam_rom_caps.hlg = 0;

	dc->caps.color.dpp.post_csc = 0;

	dc->caps.color.dpp.gamma_corr = 0;



	dc->caps.color.dpp.hw_3d_lut = 1;

	dc->caps.color.dpp.ogam_ram = 1;

	// no OGAM ROM on DCN2

	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

	dc->caps.color.dpp.ogam_rom_caps.pq = 0;

	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

	dc->caps.color.dpp.ocsc = 0;



	dc->caps.color.mpc.gamut_remap = 0;

	dc->caps.color.mpc.num_3dluts = 0;

	dc->caps.color.mpc.shared_3d_lut = 0;

	dc->caps.color.mpc.ogam_ram = 1;

	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;

	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;

	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;

	dc->caps.color.mpc.ogam_rom_caps.pq = 0;

	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;

	dc->caps.color.mpc.ocsc = 1;



	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)

		dc->debug = debug_defaults_drv;

	else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {