Commit a8648887 authored by Vladimir Oltean's avatar Vladimir Oltean Committed by David S. Miller
Browse files

net: enetc: add support for flow control 



In the ENETC receive path, a frame received by the MAC is first stored
in a 256KB 'FIFO' memory, then transferred to DRAM when enqueuing it to
the RX ring. The FIFO is a shared resource for all ENETC ports, but
every port keeps track of its own memory utilization, on RX and on TX.

There is a setting for RX rings through which they can either operate in
'lossy' mode (where the lack of a free buffer causes an immediate
discard of the frame) or in 'lossless' mode (where the lack of a free
buffer in the ring makes the frame stay longer in the FIFO).

In turn, when the memory utilization of the FIFO exceeds a certain
margin, the MAC can be configured to emit PAUSE frames.

There is enough FIFO memory to buffer up to 3 MTU-sized frames per RX
port while not jeopardizing the other use cases (jumbo frames), and
also not consume bytes from the port TX allocations. Also, 3 MTU-sized
frames worth of memory is enough to ensure zero loss for 64 byte packets
at 1G line rate.

Signed-off-by: default avatarVladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: default avatarClaudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent b764dc6c

drivers/net/ethernet/freescale/enetc/enetc_ethtool.c

+18 −0
Original line number Diff line number Diff line
@@ -708,6 +708,22 @@ static int enetc_set_wol(struct net_device *dev, 
	return ret;

}



static void enetc_get_pauseparam(struct net_device *dev,

				 struct ethtool_pauseparam *pause)

{

	struct enetc_ndev_priv *priv = netdev_priv(dev);



	phylink_ethtool_get_pauseparam(priv->phylink, pause);

}



static int enetc_set_pauseparam(struct net_device *dev,

				struct ethtool_pauseparam *pause)

{

	struct enetc_ndev_priv *priv = netdev_priv(dev);



	return phylink_ethtool_set_pauseparam(priv->phylink, pause);

}



static int enetc_get_link_ksettings(struct net_device *dev,

				    struct ethtool_link_ksettings *cmd)

{
@@ -754,6 +770,8 @@ static const struct ethtool_ops enetc_pf_ethtool_ops = { 
	.get_ts_info = enetc_get_ts_info,

	.get_wol = enetc_get_wol,

	.set_wol = enetc_set_wol,

	.get_pauseparam = enetc_get_pauseparam,

	.set_pauseparam = enetc_set_pauseparam,

};



static const struct ethtool_ops enetc_vf_ethtool_ops = {

drivers/net/ethernet/freescale/enetc/enetc_hw.h

+9 −0
Original line number Diff line number Diff line
@@ -109,6 +109,7 @@ enum enetc_bdr_type {TX, RX}; 
/* RX BDR reg offsets */

#define ENETC_RBMR	0

#define ENETC_RBMR_BDS	BIT(2)

#define ENETC_RBMR_CM	BIT(4)

#define ENETC_RBMR_VTE	BIT(5)

#define ENETC_RBMR_EN	BIT(31)

#define ENETC_RBSR	0x4
@@ -180,6 +181,8 @@ enum enetc_bdr_type {TX, RX}; 
#define ENETC_PSIVLANR(n)	(0x0240 + (n) * 4) /* n = SI index */

#define ENETC_PSIVLAN_EN	BIT(31)

#define ENETC_PSIVLAN_SET_QOS(val)	((u32)(val) << 12)

#define ENETC_PPAUONTR		0x0410

#define ENETC_PPAUOFFTR		0x0414

#define ENETC_PTXMBAR		0x0608

#define ENETC_PCAPR0		0x0900

#define ENETC_PCAPR0_RXBDR(val)	((val) >> 24)
@@ -227,6 +230,7 @@ enum enetc_bdr_type {TX, RX}; 
#define ENETC_PM0_TX_EN		BIT(0)

#define ENETC_PM0_RX_EN		BIT(1)

#define ENETC_PM0_PROMISC	BIT(4)

#define ENETC_PM0_PAUSE_IGN	BIT(8)

#define ENETC_PM0_CMD_XGLP	BIT(10)

#define ENETC_PM0_CMD_TXP	BIT(11)

#define ENETC_PM0_CMD_PHY_TX_EN	BIT(15)
@@ -239,6 +243,11 @@ enum enetc_bdr_type {TX, RX}; 


#define ENETC_PM_IMDIO_BASE	0x8030



#define ENETC_PM0_PAUSE_QUANTA	0x8054

#define ENETC_PM0_PAUSE_THRESH	0x8064

#define ENETC_PM1_PAUSE_QUANTA	0x9054

#define ENETC_PM1_PAUSE_THRESH	0x9064



#define ENETC_PM0_SINGLE_STEP		0x80c0

#define ENETC_PM1_SINGLE_STEP		0x90c0

#define ENETC_PM0_SINGLE_STEP_CH	BIT(7)

drivers/net/ethernet/freescale/enetc/enetc_pf.c

+58 −2
Original line number Diff line number Diff line
@@ -1014,7 +1014,12 @@ static void enetc_pl_mac_link_up(struct phylink_config *config, 
				 int duplex, bool tx_pause, bool rx_pause)

{

	struct enetc_pf *pf = phylink_to_enetc_pf(config);

	u32 pause_off_thresh = 0, pause_on_thresh = 0;

	u32 init_quanta = 0, refresh_quanta = 0;

	struct enetc_hw *hw = &pf->si->hw;

	struct enetc_ndev_priv *priv;

	u32 rbmr, cmd_cfg;

	int idx;



	priv = netdev_priv(pf->si->ndev);

	if (priv->active_offloads & ENETC_F_QBV)
@@ -1022,9 +1027,60 @@ static void enetc_pl_mac_link_up(struct phylink_config *config, 


	if (!phylink_autoneg_inband(mode) &&

	    phy_interface_mode_is_rgmii(interface))

		enetc_force_rgmii_mac(&pf->si->hw, speed, duplex);

		enetc_force_rgmii_mac(hw, speed, duplex);



	/* Flow control */

	for (idx = 0; idx < priv->num_rx_rings; idx++) {

		rbmr = enetc_rxbdr_rd(hw, idx, ENETC_RBMR);



		if (tx_pause)

			rbmr |= ENETC_RBMR_CM;

		else

			rbmr &= ~ENETC_RBMR_CM;



		enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr);

	}



	if (tx_pause) {

		/* When the port first enters congestion, send a PAUSE request

		 * with the maximum number of quanta. When the port exits

		 * congestion, it will automatically send a PAUSE frame with

		 * zero quanta.

		 */

		init_quanta = 0xffff;



		/* Also, set up the refresh timer to send follow-up PAUSE

		 * frames at half the quanta value, in case the congestion

		 * condition persists.

		 */

		refresh_quanta = 0xffff / 2;



		/* Start emitting PAUSE frames when 3 large frames (or more

		 * smaller frames) have accumulated in the FIFO waiting to be

		 * DMAed to the RX ring.

		 */

		pause_on_thresh = 3 * ENETC_MAC_MAXFRM_SIZE;

		pause_off_thresh = 1 * ENETC_MAC_MAXFRM_SIZE;

	}



	enetc_port_wr(hw, ENETC_PM0_PAUSE_QUANTA, init_quanta);

	enetc_port_wr(hw, ENETC_PM1_PAUSE_QUANTA, init_quanta);

	enetc_port_wr(hw, ENETC_PM0_PAUSE_THRESH, refresh_quanta);

	enetc_port_wr(hw, ENETC_PM1_PAUSE_THRESH, refresh_quanta);

	enetc_port_wr(hw, ENETC_PPAUONTR, pause_on_thresh);

	enetc_port_wr(hw, ENETC_PPAUOFFTR, pause_off_thresh);



	cmd_cfg = enetc_port_rd(hw, ENETC_PM0_CMD_CFG);



	if (rx_pause)

		cmd_cfg &= ~ENETC_PM0_PAUSE_IGN;

	else

		cmd_cfg |= ENETC_PM0_PAUSE_IGN;



	enetc_port_wr(hw, ENETC_PM0_CMD_CFG, cmd_cfg);

	enetc_port_wr(hw, ENETC_PM1_CMD_CFG, cmd_cfg);



	enetc_mac_enable(&pf->si->hw, true);

	enetc_mac_enable(hw, true);

}



static void enetc_pl_mac_link_down(struct phylink_config *config,