Commit a8588b8b authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/pm: correct VR shared rail info 



Add VR shared rail info.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5f92b48c

drivers/gpu/drm/amd/include/atombios.h

+3 −1
Original line number Diff line number Diff line
@@ -5636,7 +5636,9 @@ typedef struct _ATOM_SMU_INFO_V2_1 
{

  ATOM_COMMON_TABLE_HEADER         asHeader;

  UCHAR ucSclkEntryNum;            // for potential future extend, indicate the number of ATOM_SCLK_FCW_RANGE_ENTRY_V1

  UCHAR ucReserved[3];

  UCHAR ucSMUVer;

  UCHAR ucSharePowerSource;

  UCHAR ucReserved;

  ATOM_SCLK_FCW_RANGE_ENTRY_V1     asSclkFcwRangeEntry[8];

}ATOM_SMU_INFO_V2_1;

drivers/gpu/drm/amd/pm/inc/smu74_discrete.h

+2 −1
Original line number Diff line number Diff line
@@ -271,7 +271,8 @@ struct SMU74_Discrete_DpmTable { 


	uint8_t                             VRHotLevel;

	uint8_t                             LdoRefSel;

	uint8_t                             Reserved1[2];

	uint8_t                             SharedRails;

	uint8_t                             Reserved1;

	uint16_t                            FanStartTemperature;

	uint16_t                            FanStopTemperature;

	uint16_t                            MaxVoltage;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

+14 −0
Original line number Diff line number Diff line
@@ -1427,6 +1427,20 @@ int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctr 
	return 0;

}



int atomctrl_get_vddc_shared_railinfo(struct pp_hwmgr *hwmgr, uint8_t *shared_rail)

{

	ATOM_SMU_INFO_V2_1 *psmu_info =

		(ATOM_SMU_INFO_V2_1 *)smu_atom_get_data_table(hwmgr->adev,

			GetIndexIntoMasterTable(DATA, SMU_Info),

			NULL, NULL, NULL);

	if (!psmu_info)

		return -1;



	*shared_rail = psmu_info->ucSharePowerSource;



	return 0;

}



int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr,

				  struct pp_atom_ctrl__avfs_parameters *param)

{

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

+1 −0
Original line number Diff line number Diff line
@@ -347,5 +347,6 @@ extern int atomctrl_get_edc_leakage_table(struct pp_hwmgr *hwmgr, 
					  AtomCtrl_EDCLeakgeTable *table,

					  uint16_t offset);



extern int atomctrl_get_vddc_shared_railinfo(struct pp_hwmgr *hwmgr, uint8_t *shared_rail);

#endif

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

+14 −0
Original line number Diff line number Diff line
@@ -1016,6 +1016,16 @@ static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr, 
	return 0;

}



static void polaris10_get_vddc_shared_railinfo(struct pp_hwmgr *hwmgr)

{

	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);

	SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);

	uint8_t shared_rail;



	if (!atomctrl_get_vddc_shared_railinfo(hwmgr, &shared_rail))

		table->SharedRails = shared_rail;

}



static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)

{

	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
@@ -1041,6 +1051,10 @@ static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) 
	pp_atomctrl_clock_dividers_vi dividers;

	uint32_t dpm0_sclkfrequency = levels[0].SclkSetting.SclkFrequency;



	if (ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) ||

	    ASICID_IS_P30(adev->pdev->device, adev->pdev->revision))

		polaris10_get_vddc_shared_railinfo(hwmgr);



	polaris10_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));



	for (i = 0; i < dpm_table->sclk_table.count; i++) {