Commit a844cfbe authored by José Roberto de Souza's avatar José Roberto de Souza
Browse files

drm/i915: Skip display interruption setup when display is not available 



Return ealier in the functions doing interruption setup for GEN8+ also
adding a warning in gen8_de_irq_handler() to let us know that
something else is still missing.

Reviewed-by: default avatarRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210408203150.237947-1-jose.souza@intel.com
parent 28972f82

drivers/gpu/drm/i915/i915_irq.c

+32 −7
Original line number Diff line number Diff line
@@ -2421,6 +2421,8 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) 
	u32 iir;

	enum pipe pipe;



	drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv));



	if (master_ctl & GEN8_DE_MISC_IRQ) {

		iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IIR);

		if (iir) {
@@ -3059,14 +3061,13 @@ static void cnp_display_clock_wa(struct drm_i915_private *dev_priv) 
	}

}



static void gen8_irq_reset(struct drm_i915_private *dev_priv)

static void gen8_display_irq_reset(struct drm_i915_private *dev_priv)

{

	struct intel_uncore *uncore = &dev_priv->uncore;

	enum pipe pipe;



	gen8_master_intr_disable(dev_priv->uncore.regs);



	gen8_gt_irq_reset(&dev_priv->gt);

	if (!HAS_DISPLAY(dev_priv))

		return;



	intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);

	intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
@@ -3078,6 +3079,16 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv) 


	GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);

	GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);

}



static void gen8_irq_reset(struct drm_i915_private *dev_priv)

{

	struct intel_uncore *uncore = &dev_priv->uncore;



	gen8_master_intr_disable(dev_priv->uncore.regs);



	gen8_gt_irq_reset(&dev_priv->gt);

	gen8_display_irq_reset(dev_priv);

	GEN3_IRQ_RESET(uncore, GEN8_PCU_);



	if (HAS_PCH_SPLIT(dev_priv))
@@ -3093,6 +3104,9 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv) 
	u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |

		BIT(TRANSCODER_C) | BIT(TRANSCODER_D);



	if (!HAS_DISPLAY(dev_priv))

		return;



	intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);



	if (DISPLAY_VER(dev_priv) >= 12) {
@@ -3715,6 +3729,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) 
		BIT(TRANSCODER_C) | BIT(TRANSCODER_D);

	enum pipe pipe;



	if (!HAS_DISPLAY(dev_priv))

		return;



	if (DISPLAY_VER(dev_priv) <= 10)

		de_misc_masked |= GEN8_DE_MISC_GSE;
@@ -3798,6 +3815,16 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv) 
	gen8_master_intr_enable(dev_priv->uncore.regs);

}



static void gen11_de_irq_postinstall(struct drm_i915_private *dev_priv)

{

	if (!HAS_DISPLAY(dev_priv))

		return;



	gen8_de_irq_postinstall(dev_priv);



	intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL,

			   GEN11_DISPLAY_IRQ_ENABLE);

}



static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)

{
@@ -3808,12 +3835,10 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) 
		icp_irq_postinstall(dev_priv);



	gen11_gt_irq_postinstall(&dev_priv->gt);

	gen8_de_irq_postinstall(dev_priv);

	gen11_de_irq_postinstall(dev_priv);



	GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);



	intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);



	if (HAS_MASTER_UNIT_IRQ(dev_priv)) {

		dg1_master_intr_enable(uncore->regs);

		intel_uncore_posting_read(&dev_priv->uncore, DG1_MSTR_UNIT_INTR);