Commit a7ffb815 authored by Lucas De Marchi's avatar Lucas De Marchi Committed by José Roberto de Souza
Browse files

drm/i915/adl_s: Add power wells 



TGL power wells can be re-used for ADL-S with the exception of the fake
power well for TC_COLD, just like DG-1.

BSpec: 53597
Bspec: 49231

Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarAditya Swarup <aditya.swarup@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210129182945.217078-3-aditya.swarup@intel.com
parent b4cd8dd3

drivers/gpu/drm/i915/display/intel_display_power.c

+1 −1
Original line number Diff line number Diff line
@@ -4689,7 +4689,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) 
	 * The enabling order will be from lower to higher indexed wells,

	 * the disabling order is reversed.

	 */

	if (IS_DG1(dev_priv)) {

	if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) {

		err = set_power_wells_mask(power_domains, tgl_power_wells,

					   BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));

	} else if (IS_ROCKETLAKE(dev_priv)) {