Commit a7fa1537 authored by Radhakrishna Sripada's avatar Radhakrishna Sripada
Browse files

drm/i915/mtl: Implement Wa_14019141245 



Enable strict RAR to prevent spurious GPU hangs.

v1.1: Rebase
Bspec: 51762
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: default avatarHaridhar Kalvala <haridhar.kalvala@intel.com>
Reviewed-by: default avatarUmesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230425183011.865085-1-radhakrishna.sripada@intel.com
parent 655bd3b9

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+5 −0
Original line number Diff line number Diff line
@@ -529,6 +529,11 @@ 


#define GEN8_RC6_CTX_INFO			_MMIO(0x8504)



#define GEN12_SQCNT1				_MMIO(0x8718)

#define   GEN12_SQCNT1_PMON_ENABLE		REG_BIT(30)

#define   GEN12_SQCNT1_OABPC			REG_BIT(29)

#define   GEN12_STRICT_RAR_ENABLE		REG_BIT(23)



#define XEHP_SQCM				MCR_REG(0x8724)

#define   EN_32B_ACCESS				REG_BIT(30)

drivers/gpu/drm/i915/gt/intel_workarounds.c

+4 −0
Original line number Diff line number Diff line
@@ -1699,6 +1699,9 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 
	wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);

	wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);



	/* Wa_14019141245 */

	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);



	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||

	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {

		/* Wa_14014830051 */
@@ -1707,6 +1710,7 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 
		/* Wa_14015795083 */

		wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);

	}



	/*

	 * Unlike older platforms, we no longer setup implicit steering here;

	 * all MCR accesses are explicitly steered.

drivers/gpu/drm/i915/i915_perf_oa_regs.h

+0 −4
Original line number Diff line number Diff line
@@ -134,10 +134,6 @@ 
#define GDT_CHICKEN_BITS    _MMIO(0x9840)

#define   GT_NOA_ENABLE	    0x00000080



#define GEN12_SQCNT1				_MMIO(0x8718)

#define   GEN12_SQCNT1_PMON_ENABLE		REG_BIT(30)

#define   GEN12_SQCNT1_OABPC			REG_BIT(29)



/* Gen12 OAM unit */

#define GEN12_OAM_HEAD_POINTER_OFFSET   (0x1a0)

#define  GEN12_OAM_HEAD_POINTER_MASK    0xffffffc0