Commit a7a9d11e authored by Jerry (Fangzhi) Zuo's avatar Jerry (Fangzhi) Zuo Committed by Alex Deucher
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drm/amd/display: Update bounding box states (v2) 

[Why]
Drop hardcoded dispclk, dppclk, phyclk

[How]
Read the corresponding values from clock table entries already populated.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1403


Cc: stable@vger.kernel.org
Signed-off-by: default avatarJerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0bbf06d8

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c

+31 −10
Original line number Diff line number Diff line
@@ -2398,16 +2398,37 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params 
	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;



	if (bw_params->clk_table.entries[0].memclk_mhz) {



		if (bw_params->clk_table.entries[1].dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {

		int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;



		for (i = 0; i < MAX_NUM_DPM_LVL; i++) {

			if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)

				max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;

			if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)

				max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;

			if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)

				max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;

			if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)

				max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;

		}



		if (!max_dcfclk_mhz)

			max_dcfclk_mhz = dcn3_0_soc.clock_limits[0].dcfclk_mhz;

		if (!max_dispclk_mhz)

			max_dispclk_mhz = dcn3_0_soc.clock_limits[0].dispclk_mhz;

		if (!max_dppclk_mhz)

			max_dppclk_mhz = dcn3_0_soc.clock_limits[0].dppclk_mhz;

		if (!max_phyclk_mhz)

			max_phyclk_mhz = dcn3_0_soc.clock_limits[0].phyclk_mhz;



		if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {

			// If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array

			dcfclk_sta_targets[num_dcfclk_sta_targets] = bw_params->clk_table.entries[1].dcfclk_mhz;

			dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;

			num_dcfclk_sta_targets++;

		} else if (bw_params->clk_table.entries[1].dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {

		} else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {

			// If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates

			for (i = 0; i < num_dcfclk_sta_targets; i++) {

				if (dcfclk_sta_targets[i] > bw_params->clk_table.entries[1].dcfclk_mhz) {

					dcfclk_sta_targets[i] = bw_params->clk_table.entries[1].dcfclk_mhz;

				if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {

					dcfclk_sta_targets[i] = max_dcfclk_mhz;

					break;

				}

			}
@@ -2447,7 +2468,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params 
				dcfclk_mhz[num_states] = dcfclk_sta_targets[i];

				dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];

			} else {

				if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= bw_params->clk_table.entries[1].dcfclk_mhz) {

				if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {

					dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];

					dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;

				} else {
@@ -2462,7 +2483,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params 
		}



		while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&

				optimal_dcfclk_for_uclk[j] <= bw_params->clk_table.entries[1].dcfclk_mhz) {

				optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {

			dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];

			dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;

		}
@@ -2475,9 +2496,9 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params 
			dcn3_0_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];



			/* Fill all states with max values of all other clocks */

			dcn3_0_soc.clock_limits[i].dispclk_mhz = bw_params->clk_table.entries[1].dispclk_mhz;

			dcn3_0_soc.clock_limits[i].dppclk_mhz  = bw_params->clk_table.entries[1].dppclk_mhz;

			dcn3_0_soc.clock_limits[i].phyclk_mhz  = bw_params->clk_table.entries[1].phyclk_mhz;

			dcn3_0_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;

			dcn3_0_soc.clock_limits[i].dppclk_mhz  = max_dppclk_mhz;

			dcn3_0_soc.clock_limits[i].phyclk_mhz  = max_phyclk_mhz;

			dcn3_0_soc.clock_limits[i].dtbclk_mhz = dcn3_0_soc.clock_limits[0].dtbclk_mhz;

			/* These clocks cannot come from bw_params, always fill from dcn3_0_soc[1] */

			/* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */