Commit a7860a5f authored by Alex Elder's avatar Alex Elder Committed by David S. Miller
Browse files

net: ipa: move some GSI setup functions 



Move gsi_irq_setup() and gsi_ring_setup() so they're defined right
above gsi_setup() where they're called.  This is a trivial movement
of code to prepare for upcoming patches.

Signed-off-by: default avatarAlex Elder <elder@linaro.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 4a4ba483

drivers/net/ipa/gsi.c

+71 −71
Original line number Diff line number Diff line
@@ -198,77 +198,6 @@ static void gsi_irq_type_disable(struct gsi *gsi, enum gsi_irq_type_id type_id) 
	gsi_irq_type_update(gsi, gsi->type_enabled_bitmap & ~BIT(type_id));

}



/* Turn off all GSI interrupts initially; there is no gsi_irq_teardown() */

static void gsi_irq_setup(struct gsi *gsi)

{

	/* Disable all interrupt types */

	gsi_irq_type_update(gsi, 0);



	/* Clear all type-specific interrupt masks */

	iowrite32(0, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET);

	iowrite32(0, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET);

	iowrite32(0, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);

	iowrite32(0, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET);



	/* The inter-EE interrupts are not supported for IPA v3.0-v3.1 */

	if (gsi->version > IPA_VERSION_3_1) {

		u32 offset;



		/* These registers are in the non-adjusted address range */

		offset = GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET;

		iowrite32(0, gsi->virt_raw + offset);

		offset = GSI_INTER_EE_SRC_EV_CH_IRQ_MSK_OFFSET;

		iowrite32(0, gsi->virt_raw + offset);

	}



	iowrite32(0, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET);

}



/* Get # supported channel and event rings; there is no gsi_ring_teardown() */

static int gsi_ring_setup(struct gsi *gsi)

{

	struct device *dev = gsi->dev;

	u32 count;

	u32 val;



	if (gsi->version < IPA_VERSION_3_5_1) {

		/* No HW_PARAM_2 register prior to IPA v3.5.1, assume the max */

		gsi->channel_count = GSI_CHANNEL_COUNT_MAX;

		gsi->evt_ring_count = GSI_EVT_RING_COUNT_MAX;



		return 0;

	}



	val = ioread32(gsi->virt + GSI_GSI_HW_PARAM_2_OFFSET);



	count = u32_get_bits(val, NUM_CH_PER_EE_FMASK);

	if (!count) {

		dev_err(dev, "GSI reports zero channels supported\n");

		return -EINVAL;

	}

	if (count > GSI_CHANNEL_COUNT_MAX) {

		dev_warn(dev, "limiting to %u channels; hardware supports %u\n",

			 GSI_CHANNEL_COUNT_MAX, count);

		count = GSI_CHANNEL_COUNT_MAX;

	}

	gsi->channel_count = count;



	count = u32_get_bits(val, NUM_EV_PER_EE_FMASK);

	if (!count) {

		dev_err(dev, "GSI reports zero event rings supported\n");

		return -EINVAL;

	}

	if (count > GSI_EVT_RING_COUNT_MAX) {

		dev_warn(dev,

			 "limiting to %u event rings; hardware supports %u\n",

			 GSI_EVT_RING_COUNT_MAX, count);

		count = GSI_EVT_RING_COUNT_MAX;

	}

	gsi->evt_ring_count = count;



	return 0;

}



/* Event ring commands are performed one at a time.  Their completion

 * is signaled by the event ring control GSI interrupt type, which is

 * only enabled when we issue an event ring command.  Only the event
@@ -1878,6 +1807,77 @@ static void gsi_channel_teardown(struct gsi *gsi) 
	gsi_irq_disable(gsi);

}



/* Turn off all GSI interrupts initially; there is no gsi_irq_teardown() */

static void gsi_irq_setup(struct gsi *gsi)

{

	/* Disable all interrupt types */

	gsi_irq_type_update(gsi, 0);



	/* Clear all type-specific interrupt masks */

	iowrite32(0, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET);

	iowrite32(0, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET);

	iowrite32(0, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET);

	iowrite32(0, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET);



	/* The inter-EE interrupts are not supported for IPA v3.0-v3.1 */

	if (gsi->version > IPA_VERSION_3_1) {

		u32 offset;



		/* These registers are in the non-adjusted address range */

		offset = GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET;

		iowrite32(0, gsi->virt_raw + offset);

		offset = GSI_INTER_EE_SRC_EV_CH_IRQ_MSK_OFFSET;

		iowrite32(0, gsi->virt_raw + offset);

	}



	iowrite32(0, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET);

}



/* Get # supported channel and event rings; there is no gsi_ring_teardown() */

static int gsi_ring_setup(struct gsi *gsi)

{

	struct device *dev = gsi->dev;

	u32 count;

	u32 val;



	if (gsi->version < IPA_VERSION_3_5_1) {

		/* No HW_PARAM_2 register prior to IPA v3.5.1, assume the max */

		gsi->channel_count = GSI_CHANNEL_COUNT_MAX;

		gsi->evt_ring_count = GSI_EVT_RING_COUNT_MAX;



		return 0;

	}



	val = ioread32(gsi->virt + GSI_GSI_HW_PARAM_2_OFFSET);



	count = u32_get_bits(val, NUM_CH_PER_EE_FMASK);

	if (!count) {

		dev_err(dev, "GSI reports zero channels supported\n");

		return -EINVAL;

	}

	if (count > GSI_CHANNEL_COUNT_MAX) {

		dev_warn(dev, "limiting to %u channels; hardware supports %u\n",

			 GSI_CHANNEL_COUNT_MAX, count);

		count = GSI_CHANNEL_COUNT_MAX;

	}

	gsi->channel_count = count;



	count = u32_get_bits(val, NUM_EV_PER_EE_FMASK);

	if (!count) {

		dev_err(dev, "GSI reports zero event rings supported\n");

		return -EINVAL;

	}

	if (count > GSI_EVT_RING_COUNT_MAX) {

		dev_warn(dev,

			 "limiting to %u event rings; hardware supports %u\n",

			 GSI_EVT_RING_COUNT_MAX, count);

		count = GSI_EVT_RING_COUNT_MAX;

	}

	gsi->evt_ring_count = count;



	return 0;

}



/* Setup function for GSI.  GSI firmware must be loaded and initialized */

int gsi_setup(struct gsi *gsi)

{