Unverified Commit a752e742 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!4641 Add support for Hygon model 4h QoS

Merge Pull Request from: @hygoner 
 
Add QoS support for Hygon family 18h model 4h+ processors.

Reference:
https://gitee.com/openeuler/kernel/pulls/1531
https://gitee.com/openeuler/kernel/pulls/3836 
 
Link:https://gitee.com/openeuler/kernel/pulls/4641

 

Reviewed-by: default avatarJason Zeng <jason.zeng@intel.com>
Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents e7112d32 534ca01e
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+2 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@
#ifdef CONFIG_X86_64
# include <asm/set_memory.h>
#endif
#include <asm/resctrl.h>

#include "cpu.h"

@@ -264,6 +265,7 @@ static void bsp_init_hygon(struct cpuinfo_x86 *c)
			x86_amd_ls_cfg_ssbd_mask = 1ULL << 10;
		}
	}
	resctrl_cpu_detect(c);
}

static void early_init_hygon(struct cpuinfo_x86 *c)
+7 −3
Original line number Diff line number Diff line
@@ -834,7 +834,8 @@ static __init bool get_mem_config(void)

	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
		return __get_mem_config_intel(&rdt_resources_all[RDT_RESOURCE_MBA]);
	else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
	else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
		 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
		return __rdt_get_mem_config_amd(&rdt_resources_all[RDT_RESOURCE_MBA]);

	return false;
@@ -960,7 +961,8 @@ static __init void rdt_init_res_defs(void)
{
	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
		rdt_init_res_defs_intel();
	else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
	else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
		 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
		rdt_init_res_defs_amd();
}

@@ -991,7 +993,9 @@ void resctrl_cpu_detect(struct cpuinfo_x86 *c)
		c->x86_cache_occ_scale = ebx;
		c->x86_cache_mbm_width_offset = eax & 0xff;

		if (c->x86_vendor == X86_VENDOR_AMD && !c->x86_cache_mbm_width_offset)
		if ((c->x86_vendor == X86_VENDOR_AMD ||
		     c->x86_vendor == X86_VENDOR_HYGON) &&
		    !c->x86_cache_mbm_width_offset)
			c->x86_cache_mbm_width_offset = MBM_CNTR_WIDTH_OFFSET_AMD;
	}
}