Commit a736143a authored by Michael Ellerman's avatar Michael Ellerman
Browse files

Merge branch 'topic/ppc-kvm' into next 

Pull in some more ppc KVM patches we are keeping in our topic branch.

In particular this brings in the series to add H_RPT_INVALIDATE.
parents 4a21192e 51696f39

Documentation/virt/kvm/api.rst

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@@ -6362,6 +6362,24 @@ default. 


See Documentation/x86/sgx/2.Kernel-internals.rst for more details.



7.26 KVM_CAP_PPC_RPT_INVALIDATE

-------------------------------



:Capability: KVM_CAP_PPC_RPT_INVALIDATE

:Architectures: ppc

:Type: vm



This capability indicates that the kernel is capable of handling

H_RPT_INVALIDATE hcall.



In order to enable the use of H_RPT_INVALIDATE in the guest,

user space might have to advertise it for the guest. For example,

IBM pSeries (sPAPR) guest starts using it if "hcall-rpt-invalidate" is

present in the "ibm,hypertas-functions" device-tree property.



This capability is enabled for hypervisors on platforms like POWER9

that support radix MMU.



8. Other capabilities.

======================

arch/powerpc/include/asm/book3s/64/mmu.h

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@@ -19,6 +19,7 @@ struct mmu_psize_def { 
	int		penc[MMU_PAGE_COUNT];	/* HPTE encoding */

	unsigned int	tlbiel;	/* tlbiel supported for that page size */

	unsigned long	avpnm;	/* bits to mask out in AVPN in the HPTE */

	unsigned long   h_rpt_pgsize; /* H_RPT_INVALIDATE page size encoding */

	union {

		unsigned long	sllp;	/* SLB L||LP (exact mask to use in slbmte) */

		unsigned long ap;	/* Ap encoding used by PowerISA 3.0 */

arch/powerpc/include/asm/book3s/64/tlbflush-radix.h

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@@ -4,6 +4,10 @@ 


#include <asm/hvcall.h>



#define RIC_FLUSH_TLB 0

#define RIC_FLUSH_PWC 1

#define RIC_FLUSH_ALL 2



struct vm_area_struct;

struct mm_struct;

struct mmu_gather;

arch/powerpc/include/asm/cputhreads.h

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@@ -98,6 +98,36 @@ static inline int cpu_last_thread_sibling(int cpu) 
	return cpu | (threads_per_core - 1);

}



/*

 * tlb_thread_siblings are siblings which share a TLB. This is not

 * architected, is not something a hypervisor could emulate and a future

 * CPU may change behaviour even in compat mode, so this should only be

 * used on PowerNV, and only with care.

 */

static inline int cpu_first_tlb_thread_sibling(int cpu)

{

	if (cpu_has_feature(CPU_FTR_ARCH_300) && (threads_per_core == 8))

		return cpu & ~0x6;	/* Big Core */

	else

		return cpu_first_thread_sibling(cpu);

}



static inline int cpu_last_tlb_thread_sibling(int cpu)

{

	if (cpu_has_feature(CPU_FTR_ARCH_300) && (threads_per_core == 8))

		return cpu | 0x6;	/* Big Core */

	else

		return cpu_last_thread_sibling(cpu);

}



static inline int cpu_tlb_thread_sibling_step(void)

{

	if (cpu_has_feature(CPU_FTR_ARCH_300) && (threads_per_core == 8))

		return 2;		/* Big Core */

	else

		return 1;

}



static inline u32 get_tensr(void)

{

#ifdef	CONFIG_BOOKE

arch/powerpc/include/asm/hvcall.h

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@@ -423,9 +423,9 @@ 
#define H_RPTI_TYPE_NESTED	0x0001	/* Invalidate nested guest partition-scope */

#define H_RPTI_TYPE_TLB		0x0002	/* Invalidate TLB */

#define H_RPTI_TYPE_PWC		0x0004	/* Invalidate Page Walk Cache */

/* Invalidate Process Table Entries if H_RPTI_TYPE_NESTED is clear */

/* Invalidate caching of Process Table Entries if H_RPTI_TYPE_NESTED is clear */

#define H_RPTI_TYPE_PRT		0x0008

/* Invalidate Partition Table Entries if H_RPTI_TYPE_NESTED is set */

/* Invalidate caching of Partition Table Entries if H_RPTI_TYPE_NESTED is set */

#define H_RPTI_TYPE_PAT		0x0008

#define H_RPTI_TYPE_ALL		(H_RPTI_TYPE_TLB | H_RPTI_TYPE_PWC | \

				 H_RPTI_TYPE_PRT)