Commit a70f00e7 authored by Randy Dunlap's avatar Randy Dunlap Committed by Catalin Marinas
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Documentation: arm64: correct spelling 



Correct spelling problems for Documentation/arm64/ as reported
by codespell.

Signed-off-by: default avatarRandy Dunlap <rdunlap@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: linux-doc@vger.kernel.org
Reviewed-by: default avatarMukesh Ojha <quic_mojha@quicinc.com>
Link: https://lore.kernel.org/r/20230127064005.1558-3-rdunlap@infradead.org


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent a873bb49

Documentation/arm64/booting.rst

+1 −1
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@@ -223,7 +223,7 @@ Before jumping into the kernel, the following conditions must be met: 
  For systems with a GICv3 interrupt controller to be used in v3 mode:

  - If EL3 is present:



      - ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.

      - ICC_SRE_EL3.Enable (bit 3) must be initialised to 0b1.

      - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.

      - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across

        all CPUs the kernel is executing on, and must stay constant

Documentation/arm64/elf_hwcaps.rst

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@@ -14,7 +14,7 @@ Some hardware or software features are only available on some CPU 
implementations, and/or with certain kernel configurations, but have no

architected discovery mechanism available to userspace code at EL0. The

kernel exposes the presence of these features to userspace through a set

of flags called hwcaps, exposed in the auxilliary vector.

of flags called hwcaps, exposed in the auxiliary vector.



Userspace software can test for features by acquiring the AT_HWCAP or

AT_HWCAP2 entry of the auxiliary vector, and testing whether the relevant

Documentation/arm64/sve.rst

+2 −2
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@@ -175,7 +175,7 @@ the SVE instruction set architecture. 
When returning from a signal handler:



* If there is no sve_context record in the signal frame, or if the record is

  present but contains no register data as desribed in the previous section,

  present but contains no register data as described in the previous section,

  then the SVE registers/bits become non-live and take unspecified values.



* If sve_context is present in the signal frame and contains full register
@@ -223,7 +223,7 @@ prctl(PR_SVE_SET_VL, unsigned long arg) 
	    Defer the requested vector length change until the next execve()

	    performed by this thread.



	    The effect is equivalent to implicit exceution of the following

	    The effect is equivalent to implicit execution of the following

	    call immediately after the next execve() (if any) by the thread:



		prctl(PR_SVE_SET_VL, arg & ~PR_SVE_SET_VL_ONEXEC)