Commit a6ea1142 authored by Adrian Hunter's avatar Adrian Hunter Committed by Borislav Petkov
Browse files

perf/tests: Add misc instructions to the x86 instruction decoder test 



The x86 instruction decoder is used for both kernel instructions and
user space instructions (e.g. uprobes, perf tools Intel PT), so it is
good to update it with new instructions.

Add the following instructions to the x86 instruction decoder test:

	User Interrupt

		clui
		senduipi
		stui
		testui
		uiret

	Prediction history reset

		hreset

	Serialize instruction execution

		serialize

	TSX suspend load address tracking

		xresldtrk
		xsusldtrk

A subsequent patch adds the instructions to the instruction decoder.

Reference:
Intel Architecture Instruction Set Extensions and Future Features
Programming Reference
May 2021
Document Number: 319433-044

Example:

  $ perf test -v "x86 instruction decoder" |& grep -i hreset
  Failed to decode length (4 vs expected 6): f3 0f 3a f0 c0 00    	hreset $0x0
  Failed to decode length (4 vs expected 6): f3 0f 3a f0 c0 00    	hreset $0x0

Signed-off-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Acked-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
Acked-by: default avatarMasami Hiramatsu <mhiramat@kernel.org>
Link: https://lore.kernel.org/r/20211202095029.2165714-4-adrian.hunter@intel.com
parent 9dd94df7

tools/perf/arch/x86/tests/insn-x86-dat-32.c

+8 −0
Original line number Diff line number Diff line
@@ -2197,6 +2197,14 @@ 
"3e f2 ff 25 78 56 34 12 \tnotrack bnd jmp *0x12345678",},

{{0x3e, 0xf2, 0xff, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "jmp", "indirect",

"3e f2 ff a4 c8 78 56 34 12 \tnotrack bnd jmp *0x12345678(%eax,%ecx,8)",},

{{0xf3, 0x0f, 0x3a, 0xf0, 0xc0, 0x00, }, 6, 0, "", "",

"f3 0f 3a f0 c0 00    \threset $0x0",},

{{0x0f, 0x01, 0xe8, }, 3, 0, "", "",

"0f 01 e8             \tserialize ",},

{{0xf2, 0x0f, 0x01, 0xe9, }, 4, 0, "", "",

"f2 0f 01 e9          \txresldtrk ",},

{{0xf2, 0x0f, 0x01, 0xe8, }, 4, 0, "", "",

"f2 0f 01 e8          \txsusldtrk ",},

{{0x0f, 0x01, 0xcf, }, 3, 0, "", "",

"0f 01 cf             \tencls  ",},

{{0x0f, 0x01, 0xd7, }, 3, 0, "", "",

tools/perf/arch/x86/tests/insn-x86-dat-64.c

+20 −0
Original line number Diff line number Diff line
@@ -2495,6 +2495,26 @@ 
"c4 e2 7b 49 c0       \ttilezero %tmm0",},

{{0xc4, 0xe2, 0x7b, 0x49, 0xf8, }, 5, 0, "", "",

"c4 e2 7b 49 f8       \ttilezero %tmm7",},

{{0xf3, 0x0f, 0x01, 0xee, }, 4, 0, "", "",

"f3 0f 01 ee          \tclui   ",},

{{0xf3, 0x0f, 0xc7, 0xf0, }, 4, 0, "", "",

"f3 0f c7 f0          \tsenduipi %rax",},

{{0xf3, 0x41, 0x0f, 0xc7, 0xf0, }, 5, 0, "", "",

"f3 41 0f c7 f0       \tsenduipi %r8",},

{{0xf3, 0x0f, 0x01, 0xef, }, 4, 0, "", "",

"f3 0f 01 ef          \tstui   ",},

{{0xf3, 0x0f, 0x01, 0xed, }, 4, 0, "", "",

"f3 0f 01 ed          \ttestui ",},

{{0xf3, 0x0f, 0x01, 0xec, }, 4, 0, "", "",

"f3 0f 01 ec          \tuiret  ",},

{{0xf3, 0x0f, 0x3a, 0xf0, 0xc0, 0x00, }, 6, 0, "", "",

"f3 0f 3a f0 c0 00    \threset $0x0",},

{{0x0f, 0x01, 0xe8, }, 3, 0, "", "",

"0f 01 e8             \tserialize ",},

{{0xf2, 0x0f, 0x01, 0xe9, }, 4, 0, "", "",

"f2 0f 01 e9          \txresldtrk ",},

{{0xf2, 0x0f, 0x01, 0xe8, }, 4, 0, "", "",

"f2 0f 01 e8          \txsusldtrk ",},

{{0x0f, 0x01, 0xcf, }, 3, 0, "", "",

"0f 01 cf             \tencls  ",},

{{0x0f, 0x01, 0xd7, }, 3, 0, "", "",

tools/perf/arch/x86/tests/insn-x86-dat-src.c

+22 −0
Original line number Diff line number Diff line
@@ -1931,6 +1931,15 @@ int main(void) 
	asm volatile("tilezero %tmm0");

	asm volatile("tilezero %tmm7");



	/* User Interrupt */



	asm volatile("clui");

	asm volatile("senduipi %rax");

	asm volatile("senduipi %r8");

	asm volatile("stui");

	asm volatile("testui");

	asm volatile("uiret");



#else  /* #ifdef __x86_64__ */



	/* bound r32, mem (same op code as EVEX prefix) */
@@ -3693,6 +3702,19 @@ int main(void) 


#endif /* #ifndef __x86_64__ */



	/* Prediction history reset */



	asm volatile("hreset $0");



	/* Serialize instruction execution */



	asm volatile("serialize");



	/* TSX suspend load address tracking */



	asm volatile("xresldtrk");

	asm volatile("xsusldtrk");



	/* SGX */



	asm volatile("encls");